Modern particle accelerators[8] have very strict requirements for controlling signal. To generate signal controlling field in cavities there is a possibility to use digital vector modulator and analog upconverter[6]. Hardware circuit consists of FPGA device, digital to analog converter and low pass filter. For experiments there is also a need to design and develop measurement circuit. Same circuit could be used in final application as diagnostics module. This enables an option for constant long term measurement and fault detection. This paper presents construction of such module

Piotrowski, A

Tarnowski, S

Tarnowski, S.

Piotrowski, A.

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Digital vector modulator with diagnostic circuit for particle accelerator

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EuCARD-CON-2010-009European Coordination for Accelerator Research and DevelopmentPUBLICATIONDigital Vector Modulator with DiagnosticCircuit for Particle AcceleratorTarnowski, S (Technical University of odz) et al04 February 2010The research leading to these results has received funding from the European Commissionunder the FP7 Research Infrastructures project EuCARD, grant agreement no. 227579.This work is part of EuCARDWork Package 10: SC RF technology for higher intensityproton accelerators and higher energy electron linacs.The electronic version of this EuCARD Publication is available via the EuCARD web site<http://cern.ch/eucard> or on the CERN Document Server at the following URL :<http://cdsweb.cern.ch/record/1237830EuCARD-CON-2010-009Digital Vector Modulator with Diagnostic Circuitfor Particle AcceleratorSzymon Tarnowski, Adam PiotrowskiDepartment of Microelectronic and Computer ScienceTechnical University of Ło´dz´ul. Wolczanska 221/22390-924 Ło´dz´, Polandemail: szymon@dmcs.pl, komam@dmcs.plIndex Terms—Vector modulation, Digital modulation, Diagnos-ticsAbstract—Modern particle accelerators[8] have very strictrequirements for controlling signal. To generate signal con-trolling ﬁeld in cavities there is a possibility to use digitalvector modulator and analog upconverter[6]. Hardware circuitconsists of FPGA device, digital to analog converter and lowpass ﬁlter. For experiments there is also a need to design anddevelop measurement circuit. Same circuit could be used in ﬁnalapplication as diagnostics module. This enables an option forconstant long term measurement and fault detection. This paperpresents construction of such module.I. INTRODUCTIONModern particle accelerators have very strict requirementsfor controlling signal[2]. To satisfy this demands there is aneed to develop new kind of controlling system. In ﬁeldof generation high frequency signal there are some newpossibilities[7][4] but they have very high cost or otherdisadvantages (like signal stability, temperature instability)disqualify using them in commercial project. New research inthis area shows there is an option to generate low frequencysignal with digital modulator and then use upconversion togenerate appropriate frequency. In Fig. 1 is shown analogpart block diagram. It is single digital to analog converterLO signalmixerDAC RFoutband passFig. 1. Schematic diagram of analog part of analog upconverter(DAC) and upconversion mixer. This circuit needs a anotherreference signal (LO) with frequency higher (or lower) thandesired frequency. Because operating frequency of this circuitis about 10MHz in low frequency part and about 1.3GHz inhigh frequency part there is a need to design measurement anddiagnostics circuit.II. VECTOR MODULATORVector modulator (VM) is a device or module which gen-erate sinusoidal high frequency signal based on deliveredparameters. As input parameters amplitude and phase canbe used, but for many control systems using complex num-ber makes arithmetic operation easier. Two values, real andimaginary part of input vector combine to IQ vector. Vectormodulator can be build based on analog components, by digitalsignal synthesis or by low frequency synthesis with analogupconversion. To convert low frequency to high frequencythere is needed difrential frequency usually called by localoscillator (LO). In XFEL considered LO frequency is masteroscillator (MO) plus 9MHz or MO+13MHz. To generation of9MHz or 13MHz signal with appropriate precision there is aneed to clock circuit with 100MHz and more. Digital vectormodulators for principle operation need to calculate samplesusing invert Fourier transform. This operation needs manymultiplication so in FPGA implementation many multipliersare needed. Hardware multipliers have limited operating fre-quency, so new construction need to be developed[5]. Simpledigital vector modulator design built with counter, samplelook-up table and digital multipliers have limited operatingfrequency. The slowest part are multipliers. This problem canbe defeated with new calculation scheme, all the samples mustbe calculated before signal is generated and then sent in correctorder to DAC. Each time IQ vector changes new recalculationis needed. This will add some delay between IQ vector changeand output signal update. Calculation of this delay will beshown later. For faster operation lookup table with calculatedsamples is constructed as circular buffer. When new data isready multiplexer select new data, after loading time, circularbuffer is operating normally.A. Block diagram and state diagramBlock diagram shown in Fig. 2 consists of following com-ponents:• Machine, Finite State Machine (FSM), control and timingblock• Comparator, compares current IQ vector with input IQvector• Multiplexer, selects which data load into shifter (new orold)Fig. 2. Block Diagram• Calculator, calculate new values of samples from IQvector and stored internally sine and cosine tables• Loader and Shifter, shifting registers• Cache, temporary register for storing current IQ vectorFig. 3. State DiagramState diagram is shown in Fig. 3, when the vector modulatorstarts, waits for new IQ vector. When value of current IQvector is different than IQ vector stored in cache register (at thestart reseted to zero), calculation process begins. The sampleupdate process consists of following steps:1) UPLOAD New IQ vector is stored in cache register,takes 1 cycle2) CALCULATE Calculation of samples, in parallel allsamples are calculate, takes at least 1 cycle, depends onmultipliers in FPGA3) LOAD New samples are loaded parallel into Loaderregister, takes 1 cycle4) SYNC FSM waits for synchronization between shiftercurrent state and ﬁrst sample of output signal period,time variable, takes at least 1 cycle, up to to number ofsamples per period cycles5) LOAD WAIT FSM waits until all samples from loaderare stored in shifter, takes number of samples per periodcycles6) READY FSM ends operation, and waits for new data,data to DAC is sent via circular buffer, state is stableuntil IQ Vector updateIII. VM IP CORE FEATURESVector modulator was written in VHDL language and pre-pared as complete module (IP core).A. Flexible conﬁgurationFig. 4. VM IP Core deﬁnitionVHDL entity is internal conﬁgurable. VHDL entity deﬁni-tion is shown on Fig. 4 There are 3 parameters:• NUMBER OF SAMPLES PER PERIOD, number ofsamples per period of output signal• NUMBER OF BITS PER SAMPLE, number of bitsper one sample (sample width)• NUMBER OF BITS PER IQVALUE, number of bitsper one variable of vector (I or Q)B. VHDL sample value calculationVM IP core during VHDL synthesis calculate itself samplesof sine and cosine. In synthesis output there is added fordebugging dump of values in real, integer and binary format.Exemplary debug is shown on Fig. 5.Fig. 5. Exemplary sine sample calculationC. Update delayDelay between new IQ vector and output signal change isvariable, but can be calculate according equationTupdate = Tready + Tupload + Tcalculate + Tload + Tsync +Tload wait where:• Tready = 1 Tcy• Tupload = 1 Tcy• Tcalculate = 1 Tmul• Tload = NUMBER OF SAMPLES PER PERIOD Tcy• Tsync = 1 . . . NUMBER OF SAMPLES PER PERIODTcy• Tload wait = NUMBER OF SAMPLES PER PERIODTcywhere:Tcy equals time between clock cycles ( 1Fclk )Tmul equals time of asynchronously working multiplier timeof calculation (depends on FPGA architecture)D. Operating frequencyTo test described project, there were made laboratory ex-periments using MEMEC Virtex2P test-board. For synthesisand implementation Xilinx ISE v9.0 was used. First test weremade in very low clocking frequency (about 1Hz) to testmachine operation. Input data (IQ vector) was set as table of4 values which were selected asynchronously by dip-swiches.Circuit was checked with LED connected to debug output.State changes presented by LED were exactly as designed. Forﬁnal test, clocking was from integrated oscillator multiplied bydigital clock manager (DCM). Synthesizer timing commentsare shown on Fig. 6. Synthesis was made for FPGA Virtex2P,which has internal multipliers capable of running at about100MHz. This design is runing up to 250MHz. Implementa-tion was tested up to 200MHz on Memec board. Project wasnot operating at 250MHz, probably due to DCM limitation orpoor clock routing on the test board.Fig. 6. Xilinx ISE timing reportIV. DIAGNOSTIC CIRCUITTo test operation diagnostic circuit was designed. Thissubsystem can be divided into two parts. The ﬁrst one is analogpart and the second one is digital acquisition circuit. Beforecircuit design there were following requirements deﬁned:• High input impedance• Capability to drive 50Ω input• Monitoring output• Low pass analog ﬁlters (about 13MHz) with bypassoption• Variable attenuator with bypass option• Low frequency root mean square amplitude measurement(TrueRMS)• High frequency power measurement (in external module)V. ANALOG SYSTEMFor experiments diagnostic circuit was integrated with ana-log ﬁlters on one board. Filters were designed with fastoperational ampliﬁers (Analog Devices AD8014). Forth orderlow pass ﬁlter (two steps) was calculated as Butterworthﬁlter. Values were tested in Spice program. Calculated cutofffrequency was set at 13MHz. Measured characteristic is shownin Fig. 7. To maximize amplitude characteristic of frequencyFig. 7. Measured ﬁlter characteristicsmixer (below compression point) and reduce gain ripple therewas a need to add variable attenuator in board. For this wasselected digital potentiometer (MAXIM DS1267) controlledby system. This component has small bandwith, but if addsome external components it is possible to extend bandwidth[1]. This will limit range of regulation, but in this circuit fullrange regulation is not necessary. Board consists also of outputbuffer for driving 50Ω input of mixer, relays bypassing ﬁlterand attenuator and also TrueRMS (Analog Devices AD637)converter with signal conditioning ampliﬁer. Signal condition-ing ampliﬁer is needed because used TrueRMS converter isworking near to its bandwidth limit. Block diagram of analogpart is shown in Fig. 8.VI. CONTROL AND ACQUSITION SYSTEMAcquisition system consists of two parts. The ﬁrst oneis hardware board with micro-controller. The second one issoftware for PC computer.A. Hardware boardHardware board is based of 8-bit micro-controller (Mi-crochip PIC18F4523) with build in 12bit ADC. Communica-tion between PC computer and board is made with EIA-232interface. To achieve precision and recurrence external preci-sion voltage reference source was added (Texas InstrumentsREF3040).mixerLOinputBypass 1 Bypass 2variable13MHz BufferRMSconvinput filter atten.PWRconvRFoutcouplerFig. 8. Analog system block diagramPIC18F uP EIA-232PowerVrefconverterSupplyADC1ADC2ADC3 ADCVrefAnalog BoardcontrolFig. 9. Block diagram of daq boardB. PC applicationTo control device and read values from simple applicationwas developed. Program was written under Borland Delphienvironment. Application interface is shown in Fig. 10. ToFig. 10. Application screen-shot (interface in Polish language)increase precision of measurement application makes multiplemeasurements and averages values.VII. CONCLUSIONPresented solution was tested in laboratory and proved itsoperatibility. Proposed circuits could be implemented in ﬁnalversion of system integrated on ATCA[3] board or AMCmodule. Active ﬁlter based on discreete components doesnot have enough slope for this application. There are twopossibilities how to deal with this problem. The one solutionis to increase clocking frequency and the second one is to usepassive ceramic ﬁlters with high Q-factor.ACKNOWLEDGMENTSThe research leading to these results has received fundingfrom the European Commission under the EuCARD FP7Research Infrastructures grant agreement no. 227579.The author is a scholarship holder of project entitled ”In-novative education ...” supported by European Social Fund.The work was supported by the Ministry of Science andHigher Education (grant agreement no. 2273/B/T02/2008/35).REFERENCES[1] Maxim Integrated Products. Application Note 3081: How to Increase theBandwidth of Digital Potentiometers 10x to 100x. 2004.[2] S. Simrock. Achieving phase and amplitude stability in pulsed super-conducting cavities. Technical report, Deutsche Elektronen-SynchrotronDESY, 2001.[3] S. Simrock. Requirements for the ATCA based LLRF Evaluation System.In Review of LLRF system based on ATCA standard, 8-9 Nov 2007.[4] Sz. Tarnowski. High frequency signal synthesis for particle acceleratorcontrol. IX International PhD Workshop OWD’2007, 20-23 October 2007.[5] A. Piotrowski Sz. Tarnowski. Uniwersalny modulator wektorowy synte-zowalny do ukadu fpga. Reprogramowalne Ukady Cyfrowe, RUC 2008,2008.[6] Sz. Tarnowski, A. Piotrowski. Application of precision low frequencysignal generation as intermediate frequency for upconversion in particleaccelerator ﬁeld control. MIXDES 2008.[7] Sz. Tarnowski, A. Piotrowski, A. Napieralski. Direct digital modulationsystem for LLRF. IEEE-SPIE WILGA 2007.[8] Tesla collabolation members. A Proposal to Construct and Test PrototypeSuperconducting RF Structures for Linear Colliders. Technical report,CERN/DESY/FERMILAB, 1993.

Digital Vector Modulator with Diagnostic Circuit for Particle Accelerator

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Digital Vector Modulator with Diagnostic Circuit for Particle Accelerator

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