The problem of translating the time of occurrence of received Loran-C pulses into a time, referenced to a particular period of occurrence is addressed and applied to the design of a digital word generator for a Loran-C sensor processor package. The digital information from this word generator is processed in a KIM-1 microprocessor system which is based on the MOS 6502 CPU. This final system will consist of a complete time difference sensor processor for determining position information using Loran-C charts. The system consists of the KIM-1 microprocessor module, a 4K RAM memory board, a user interface, and the Loran-C word generator

Nickum, J. D.

English

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TECHNICAL MEMORANDUM (NASA) 54
LORAN-C DIGITAL WORD GENERATOR FOR USE WITH
A KIM-1 MICROPROCESSOR SYSTEM
The digital word generator used with
Mini-L front end to develop a Loran
sensor prnccssar at Ohio University
is described.
by
s^
James D. Nickum
Avionics Engineering Center
Department of Electrical Engineering
Ohio University
Athens, Ohio 45701
(NASA—C11- 1553C4) 	 LCItiAN —C D161 'AL WCHC
Gt NE[, Ar 0P FOF USE WITH A KIM-1 14 p 11CMI^:kCPFCCFSSCE SY`TEM (chin U[iv.) 	
CSCi. 17G
A02 1"F A01
December 1977
18-17032
:1nCIdS
G3/04 02601
Supported by
National Aeronautics and Space Administration
Langley Research Center
Hampton, Virginia
Grant NCR 36-009-017
1978
.Jt'I
^r
TABIE OF CONTENTS
PAGE
I	 INTRODUCTION	 1
II	 OVf RALL CIRCUIT DESCRIPTION	 1
III	 DETAILED CIRCUIT DESCRIP T ION	 1
IV	 TESTING AND VERIFYING THE INTERFACE 	 2
V	 SUMMARY
	
2
VI	 REFERENCES	 2
VII	 APPENDICES
A. Software Listing of Verification Routine	 10
B. Parts List for Interface 	 12
a 1 _--
INTRODUCTION
The process of converting analog events to a digital form is a problem whenever
information i-. 10 be processed by a digital computer. This report will address itself to the
problem of translating the time of occurrence of received Loran-C pulses into a time,
referenced to a particular period of occurrence.
This digital word generator is designed as part of a Loran-C sensor processor package
being developed at Ohio University under the NASA Tri-University Program. The digital
infurmation from this word generator is processed in a KIM-1 microprocessor system which
is based on the MOS 6502 CPU.
This final system will consist of a complete time difference sensor processor for
determining position informution using Loran-C charts. The system consists of the KIM-1
microprocessor module, a 4K RAM memory hoard, a user interface and the Loran-C word
generator described in this report.
II.	 OVERALL CIRCUIT DESCRIPTION
In describing ti,e interface refer to the overall circuit block diagram, Figure 1 .
The complete word generator is memory-mapped to the CPU. All information transfers under
control of the CPU via address and data busses. The interface therefore appears as memory
to the CPU.
The counter block is a six-digit BCD counter that is incremented at a 1 16 rate.
The complete counter is reset to zero by the GRI reset logic every 99300 Ns. This corresponds
to the GRI rate of the East Coast Loror,-C chain. The present counter output is always
available to the tristate latches.
Referring to the control logic, a 10 E n TTL compatible pulse generated by the Mini-L
front end, as described by Burhans III , is the input to the 'nterface. The leading edge of
this 10 fa pulse from the front end also generates an interrupt to the processor which then
through memory-mopped addressing reads three bytes of data from the interface.
There are two control flags that are software driven and control the output of The
interrupt from the interface and the control of the GRI sync feature of the counters. These
flags were provided to allow software flexibility in the sensor processor programs.
Ill.	 DETAILED CIRCUIT DESCRIPTION
Referring to Figure 2, a detai led schematic of the interface, devices U1-U5 are BCD
counters. They are connected in a count-up scheme and clocked by the buffered 1 MHz
system clock from U18a. The counter clear inputs are all tied to the output of U17b-9. The
flip flop Ul'7b, the diodes at U15 and the GRI sync enable flag output U20-10 comprise the
GRI sync logic.	 If the GRI sync flag is low, then U17b-9 will be kept low and this will
allow the counters to freerun. If the GRI sync flag is high, then as the counter increments
to 99300F6, the diode decoder will clock U17h-9 high which will clear all the counters.
When the MSB of U1 goes low, this resets U17h and the cycle will repeat again.
The control logic is composed of U16a,b; Ul7a; U18a,b,c; U12b. Referring to the
timing diagram of Figure 3, we see that this logic is responsible for the syncronization of
the incoming lops pulse from Mini-L. It also assures that one and only one interrupt pulse
	
will	 be generated.	 In addition it generates the clock pulse for the trktate latches to
ck; -:k the data from the counters into the latches. Finally it provides a flag input from the
CPU to enable or disable the Loran interrupts.
The address decoding is provided by U6; U18d,e,f; U12a,c,d. The device that
simplifies the decoding is the 74LS138 decoder U6. Devices U18d,e and U12a,c provide
a hexadecimal decoding of 3XXX, where the X's are a don't care value. This output along
with 02 enables the decoder 06 and finally provides unique outputs for 3XX0, ^XX1, 3XX2
used as read only and 3XX3 is used as write only. Referring to Figures 5 and 6 131, which are the
6502 CPU input and output'iming relationships, we can assume the following and allow the
decoder U6 to be used as a read and write decoder wi thout read and write steering loci, c .
If we define locations 3XX0 -3XX2 for read only and 3XX3 for write only and we user 02 as
the decoding enable (rising edge clocking edge and low time as enable), we can see that
no bus conflict will occur and there is no need to steer the read write signals. This scheme
was used because it simplifies the common logic otherwise requ'red 4f we were to say read
and write on each individual decoder select outp it.
The control flag logic is simply an 8-bit latch that is enab led by the decoder output
and clocked by the rising edge of 4)2.
IV. TESTING AND VERIFYING THE INTERFACE
To test the interface an interrupt process routine was written that would service the
interrupt, get the data and display it on the KIM-1 display. Appendix A contains the soft-
ware listing. Figure 7 is a basic flowchart of the testing routine. This routine is built
around some of the display subroutines contained in the KIM-1 monitor(21 . The testing
routine allows, along with the Mini-L front end, the observation of waveforms on an osci llo-
scope to verify the timing and,therefore,proper operation of the word generator. This routine
can also be used as a qualitative test of the Mini-L frost end, Loran-C word generator acid
the KIM-1 microprocessor system.
V. SUMMARY
In conclusion the Loran-C word generator described in this report has been bui It
and is operating on a KIM - 1 microprocessor system. This interface is by no means a unique
or ultimate solution bu t itaccomplisl.es present goals in developing Loron - C sensor processor
techniques at Ohio University. (See Figures 8 and 9 for photographs of the system).
VI. REFERENCES
	
1 j	 MINI-L LORAN-C RECEIVER, R.W. Burhans, NASA Tl,.l 48, March 1977.
	
2	 KIM-1 MICROCOMPUTER MODULE USER MANUAL, MOS Technology, Inc.,
August 1976.
( 3 J MCS6500 MICROCOMPUTER FAMILY PROGRAMMING MANUAL, MOS
Technology, Inc., Januury 19M.
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- 7-
START
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ENAQLL
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DISPLAY
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READ DATA
FROM INTERFACE
STORE TO
DISPLAY
Figure 7. Interrupt How Chart.
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Figure 9. Complete Digital Signal Processor, Loran Word Generator Board on
Left, KIM-] Microprocessor on Right.
—9—
VII.	 APPENDICES
A.	 Software listing of Verification Routine.
-10-
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1380
1380
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139D 4C 9A 13
13A0 A9 02
13A2 UD 03 30
13A5 AD 02 30
13AO 85 F9
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13AD 85 FA
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13B4 O5 FD
13D6 A9 06
1308 HD 03 30
13BB 40
8
2
3
4
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8
9
10
11
12
13
14
15
16
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19
20
21
22
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25
26
27
28
29
30
31
32
33
34
35
36
32
30
39
40
41
42
43
44
45
46
47
40
49
50
51
5?
INTERUPT SERVICE ROUTINE BEGINS HERE
*
*
^
LIRQ LDA =I%SO
STA CONTRL DISABLE INTERFACE TNTFRUPTS
LDA LMR3 GET LSD OF T1ME
STA DISP1 SAVL IN DISPLAY
LDA LUR2 GET NSB OF TIME
STA DISP2 SAVE IN DISPLAY
LDA LORI OUT MGB OF	 TIM!,
AND =$0F MASK OFF TOP HALF DY[[
STA DISP3 SAVE IN DISPLAY
LDA =JOSO
STA CONTRL ENABLE lNT[RFACK	 IN/|RUPTS
KTi R[[i|RN FkUM INTUX}[|
END
[XLCUl|(IN PL-6100^9^
END PASS I :	 () LWWWWS
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Tw0 RnmDM[ wT|| 'TrsT AND VERIFY 7111' 1hRAN C
WORD GI EN[RA7V^^, T|IE GIA|/7 ADDRESS %!. $1382^
TWE PROGRAM W%Ll. RUN U0lIL HAI ' TFD ^ XI rH[
HARDWARE IU QPDRA![MG [)111 / ` '`:'|AY W11 
It. ICKLR TH[ JW|'U? DATA. IF '.'| ..| (MEN |S
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PROBLEM IN NARDWAkE^
'11-IE F0i|OWING ARE AVORE96IWG AND DA/A
DFFINTYIWNS"
IN|ERUPT ON SYNC QA
IN/[RUPT ON SYNC 01 
YniENUPT OFF SYNC ON
%N[LRUPT 01  SYNC OFF
*	 PROGRAM BEGINS ||LRE
*
S[I l/IGADLE	 %N/[kUPTS
LOA =IXSO DISABLE INTERFACE ]N[EF^UPTS
STA CQWTkL
LDA XIRQfl GET MSn OF 	 INTERUPT VECTOR
STA IRQLf1 SF[ INT[|<UPT vEC[UR MSR
LOA XJRQ GLT LSD INTERUPT VECTOR
STA IRQL SET INTERUPT VECTOR LSQ
CLI CLEAR CPU INTERUPT DISABLE
LDA =IOSO
STA CON[RL ENABLE INTERFACE IN[ERUPTS
JSR SCANDS LOOP IN DISPLAY ROUTINE
.1MP LOOP
ORC $13b0
]UuO FW|| 06
IOU EWU 04
%xuQ [QU 02
IxSx ED(| 00
SCANDS EQU $1[1F
CONrRL FU" $3003
LORI EUU $3000
LOR2 EQU $3001
LOR3 ED(| $3002
IROL ED" $17FE
DISP1 EQd $OOF9
QISP2 [DU $OOF#
D[SP3 LOW $OOFS
X1kW ADR LIkQ
*
[// PASS 7:	 0 ERRORS
R ;
B.	 Parts List for Interface.
1	 U 14,	 U2 , U 3, U4 , U 5 74 L5193
2	 U7, U8, U9, U10, Ull 4076
3	 U6 74 L S 138
4	 U12 74 LS00
5	 U18 74 LS 04
6	 U16, U17 7474
7	 U i 9, U20 74175
8	 Diodes IN4148
-12-


Loran-C digital word generator for use with a KIM-1 microprocessor system

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