Multilayer Techniques to Address Parameter Variation

Abstract

As integrated-circuit technology continues to scale, process variation is becoming an issue that cannot be ignored at the microarchitecture and system levels. Process variation is particularly detrimental to a processor's frequency and leakage power. To solve this growing problem, solutions at different levels of the computing stack are needed. This thesis presents a couple of such solutions. The first solution, is a circuits technique that has important implications on the microarchitecture. It is based on the previously-proposed Fine-Grain Body Biasing (FGBB), where different parts of the processor chip are given a voltage bias that changes the speed and leakage properties of their transistors. Previous work proposed determining the optimal body bias voltages at manufacturing time and setting them permanently for the lifetime of the chip. In this thesis, I propose a new technique (called Dynamic FGBB - D-FGBB), which allows the continuous re-evaluation of the bias voltages to adapt to dynamic conditions. Within-die process variation causes individual cores in a Chip Multiprocessor (CMP) to differ substantially in both static power consumed and maximum frequency supported. In this environment, ignoring variation effects when scheduling applications or when managing power with Dynamic Voltage and Frequency Scaling (DVFS) is suboptimal. This thesis presents a set of variation-aware algorithms for application scheduling and power management. One such power management algorithm, uses linear programming to find the best voltage and frequency levels for each of the cores in the CMP ??????maximizing throughput at a given power budget