Cheung, PYK

Constantinides, GA

Sidahao, N

English

Sidahao, Nalin

Constantinides, George A

Cheung, Peter YK

Spiral - Imperial College Digital Repository

A Heuristic Approach for MultipleRestricted MultiplicationNalin Sidahao, George A. Constantinides, and Peter Y. K. CheungDepartment of Electrical & Electronic Engineering,Imperial College, London, UK,Email: {nalin.sidahao, g.constantinides, p.cheung}@imperial.ac.ukAbstract— This paper introduces a heuristic solution to themultiple restricted multiplication (MRM) optimization problem.MRM refers to a situation where a single variable is multipliedby several coefficients which, while not constant, are drawnfrom a relatively small set of values. The algorithm involvesderiving directed acyclic graphs representing multiple constantmultiplication obtained for each time step and then merging thesegraphs into a single MRM graph. For FPGA implementation, theproposed approach results in significant area savings, especiallyfor large problem sizes, and is time-efficient compared to aprevious optimum approach using Integer Linear Programming.I. INTRODUCTIONMany Digital Signal Processing (DSP) or arithmetic-intensive applications involve frequent use of multiplication.The multiplication operation is considered to be expensive,as it consumes significant logic and routing resources forimplementation. For constant multiplications, it is commonto use a combination of shift-and-add operations rather thanusing full multipliers, to reduce the hardware usage [1]. Sincethe shift operation can be implemented by wiring, it hasnegligible cost in a bit parallel implementation. Therefore, thetotal hardware cost approximately corresponds to the area ofthe adders required.For the problem of multiple constant multiplication (MCM),common sub-expression elimination (CSE) can be applied toa set of constant multipliers in order to minimize the numberof additions required [2], [3].This paper introduces a heuristic approach to a related prob-lem, the recently proposed multiple restricted multiplication(MRM) optimization [4]. MRM refers to a situation wherea single variable is multiplied by several coefficients that,while not constant, are drawn from a finite set of constantsthat change with time. Such a situation arises commonly inhigh level synthesis tasks due to resource sharing, for examplein a folded implementation of a FIR filter [5] or polynomialevaluation [6], [7].In summary, the main contributions of this paper are:• A novel heuristic for the multiple restricted multiplicationproblem.• FPGA implementation comparisons between the pro-posed approach, a standard approach, and the optimalapproach previously published [4].The remainder of this paper is structured as follows. Section2 of introduces the proposed heuristic, Section 3 presents theresults compared both a standard alternative implementation,and a previous optimal approach, and Section 4 concludes thepaper.II. PROPOSED HEURISTICExisting synthesis approaches to CSE are unable to takeadvantage of the MRM situation, resulting in the use ofexpensive general multipliers, as shown in Fig. 1. Fig. 1(a)shows a Data Flow Graph (DFG) containing two multiplierswith a common input x, and sets of constant multiplicandslabelled as {c11, c12, . . . , c1T } and {c21, c22, . . . , c2T }. Thefirst subscript here refers to the spatial index and the secondto the time index, i.e. cit is the value of multiplicand i at timet. A standard implementation using ROMs and multipliers isdepicted in Fig. 1(b).x{c11, c12,… , c1T}y1 y2xy1 y2c21c22...c2Tc11c12...c1TROM ROM{c21, c22,… , c2T}(a) (b)Fig. 1. (a) The DFG of a simple MRM problem. (b) The standardimplementation with ROMs and multipliers.In [4], it was shown that the MRM problem can be ad-dressed through extending the basic unit of operation from anaddition, used in MCM, to an adder/multiplexer combinationshown in Fig. 2(a). It was further demonstrated that forXilinx-based implementations, the Xilinx Virtex / Virtex-IIslice architecture [8] can be used to implement such a basiccomputational unit with no area overhead compared to theequivalent adder used in MCM.As an example, assume we have a single variable inputx multiplied by two sets of coefficients {165, 132, 32} and{40, 32, 8}. An optimized implementation of this MRM prob-lem can be seen in Fig. 2(b), and is described below.Fig. 2(b) is recognizable as a standard MCM solution,containing two addition nodes [9], and generating the twovalues 165x and 40x. Figs. 2(c) and (d), illustrate how thesame DFG structure, can be used to obtain the remaining6920-7803-8834-8/05/$20.00 ©2005 IEEE.(a)basca, b : inputc : outputs : selector253253165 40253x x xy1 y2 y1 y2 y1 y2(10100101) (00101000)132 32(10000100) (00100000)32 8(00100000) (00001000)(b) (c) (d)Fig. 2. (a) An adder/multiplexer node, and configurations to create thecoefficient sets {165, 132, 32} and {40, 32, 8} in (b) 1st time step, (c) 2ndtime step, and (d) 3rd time step. (Black dots represent left-shift operations)coefficients, by selecting the behaviour of the nodes from thepossibilities shown in Fig. 2(a).In general, we may encode an instance of the MRM problemas a T ×C matrix, where T is the number of rows correspond-ing to time steps and C is number of columns representingdistinct outputs. For example, Fig. 2 is a 3 × 2 problem.The question arises: how many computational nodes are re-quired for a given MRM problem? The authors have previouslypresented an approach to find solutions to the minimum-costof this optimization problem by formulating it as an IntegerLinear Program (ILP) [4]. However the solution time requiredfor this ILP increases rapidly with the problem size, and inpractice this approach is unsuitable for solving MRM problemswith more than three time steps or three outputs. This is themotivation for the heuristic presented in this paper.The proposed methodology involves the merging of severaldirected acyclic graphs (DAGs), one per time-step, where eachnode represents an addition operation, into a single MRMgraph.A. Generating MCM GraphsThe first step of the algorithm is therefore to generate thegraphs for each time-step. This is multiple constant multipli-cation (MCM) problem, for which there are many known ap-proaches. Our synthesis system follows the algorithm proposedin [9], summarized as follows for convenience. 1. Reduce allcoefficients to their equivalent odd ‘fundamental’, by repeateddivision by two. 2. Remove repeated fundamentals and theunit fundamental, as these does not incur implementation cost.3. Create a graph with the remaining cost-1 fundamentals asnodes. 4. Try to form remaining fundamentals through pair-wise sums of form x + 2kx or x + 2ky, where x and y areexisting nodes, and k is a positive integer. 5. Repeat (4) untilno more possible. In case this procedure does not produceall required coefficients, it is required to introduce additionalnodes and repeat (see [9] for details). As a simple example,assume we have a 3 × 3 problem⎛⎝16 23 3528 11 1428 34 33⎞⎠.The MCM graphs for each time step are depicted in Fig. 3.011123452011233 2011322154(a) (b) (c)Fig. 3. The MCM graphs for (a) {16, 23, 35}. (b) {28, 11, 14}.(c) {28, 34, 33}.B. Graph MergingThe novelty of the proposed approach comes in the merg-ing of these MCM graphs to form a single implementationstructure for the MRM problem. One can imagine that findingan MCM graph for a particular time step within an MRMgraph is similar to subgraph isomorphism [10], which involvesmapping of a graph into a subgraph of another having the samestructure.However the proposed process is different in that a path ofthe MRM graph can be mapped onto an edge of the othergraph, in such a way that sum of the weight of edges in thepath is equal to the weight of that edge. This path correspondsto a path through multiplexers in the MRM implementation.The process of merging is shown in Algorithm GraphMapping, but before describing the algorithm, it is instructiveto consider an example.An example of merging the MCM graphs in Fig. 3 isillustrated in Fig. 4 and Fig. 5. The procedure starts bychoosing one of the MCM graphs as the core MRM graph,which is then expanded as necessary. Let us take Fig. 4(a)as the MRM graph L, and and 4(b), as the MCM graph S.These figures illustrate how nodes 1 and 3 of each graph can bematched together with the corresponding node 1 and 3 of theother graph. Consider node 3, where the dashed line in Fig. 4represents the path 〈3, 2, 0〉, which has the same weight asthe edge 〈3, 0〉 in Fig. 4. Similarly, the dotted path representsanother mapping, between the path 〈3, 1〉 and the edge 〈3, 1〉.The result of graph merging is depicted in Fig. 4(c), where anextra node 5 has been introduced to account for the unmappedportion of Fig. 4(b), i.e. node 2.The process is then repeated, trying to add the MCM graphof Fig. 5(b) to the result of the previous phase, illustrated againin Fig. 5(a). Nodes 1 and 2 in Fig. 5(b) can be matched tonodes 1 and 5, respectively, in Fig. 5(a). The final minimizedMRM graph is shown in Fig. 5(c).Algorithm Graph Mapping, which performs this processautomatically, consists of 5 recursive subroutines: Main Map,693011123452011233 201112345252(a) (b) (c)Fig. 4. Graph merging (a) the initial MRM graph, (b) the MCM graph tobe added, and (c) the result of merging.01112345252011123452612501132215457(a) (b) (c)Fig. 5. Further graph merging (a) the MRM graph resulting from the previousmerging process, (b) the MCM graph to be added, and (c) the result ofmerging.Map Inedge, Check Start Nodes, Check Weights, andCheck Zero Weight. The algorithm takes as input graphs Land S, together with the source node s0 and l0 of L andS, respectively. It then proceeds to systematically search theedges of L from every computational node l back to l0, andl is said to be ‘matched’ to a node s when there is a set ofpaths in the graph L, for which each element can be mappedan edge in the path from s0 to s.In algorithm Graph Mapping below, if Main Map(s, l) eval-uates to TRUE, then we record that node l can be mappedto node s by setting mark node match[s][l]. Main Map triesto build a correspondence between two nodes l and s in theMRM and MCM graphs, respectively. Algorithm Map Inedgeperforms mapping a path l to an edge s, the central differencebetween this procedure and one for subgraph isomorphism.Subroutine Check Start Nodes checks whether each node sand l has reached the graph source nodes s0 and l0. AlgorithmCheck Weights is called whenever both edges of node land s has its same predecessor, in order to ensure that thepath weight is correct. Finally, Algorithm Check Zero Weightsearches an edge of l that has zero weight and then considerits predecessor with s by calling Main Map algorithm.Algorithm Graph MappingInput: Two Computational MCM Graphs L and SOutput: An MRM Graphbeginmark node match[l][s] ← FALSE for all l ∈ L, l = l0, s ∈ S, s = s0foreach s ∈ S doforeach l ∈ L doif Main Map(l, s) domark node match[l][s] ← TRUEend ifend foreachend foreachendMain MapInput: Two Computational Nodes l and sOutput: TRUE if node l can be mapped to s, FALSE otherwisebeginif pred1(l) = pred2(l) && pred1(s) = pred2(s) doreturn (Map Inedge(inedge1(l), inedge1(s), w(inedge1(s)))&& Map Inedge(inedge2(l), inedge2(s), w(inedge2(s))))‖ (Map Inedge(inedge1(l), inedge2(s), w(inedge2(s)))&& Map Inedge(inedge2(l), inedge1(s), w(inedge1(s))))else if pred1(l) = pred2(l) && pred1(s) = pred2(s) doreturn Check Zero Weight(w(inedge1(l)), w(inedge2(l)))else if pred1(l) = pred2(l) && pred1(s) = pred2(s) doreturn Check Weights(inedge1(l), inedge2(l), inedge1(s), inedge2(s))elsereturn FALSEend ifendMap InedgeInput: inedgex(l), inedgex(s), wxOutput: TRUE if inedgex(l) can be mapped to inedgex(s), FALSE otherwisebeginwdif = wx − w(inedgex(l))if wdif = 0 doreturn Check Start Nodes(inedgex(l), inedgex(s))else if wdif > 0 doif predx(l) = l0 doreturn Map Inedge(inedgex(l), inedge1(predx(s)), wdif )‖ Map Inedge(inedgex(l), inedge2(predx(s)), wdif )elsereturn FALSEend ifelsereturn FALSEend ifendCheck Start NodesInput: inedgex(l), inedgex(s)Output: TRUE if inedgex(l) can be mapped to inedgex(s),or both predx(l) and predx(s) reach their start nodes, FALSE otherwiseif predx(l) = l0 && predx(s) = s0 doreturn Main Map(predx(s), predx(l))else if predx(l) = l0 && predx(s) = s0 doreturn Map Inedge(inedgex(s), inedge1(predx(l)), 0)‖ Map Inedge(inedgex(s), inedge2(predx(l)), 0)else if predx(l) = l0 && predx(s) = s0 doreturn TRUEelsereturn FALSEend ifendCheck WeightsInput: inedge1(l), inedge2(l), inedge1(s), inedge2(s)Output: TRUE if weight edges can be mapped and Check Start Nodes returns TRUE,FALSE otherwisebeginif ((w(inedge1(l)) = w(inedge1(s)) && w(inedge2(l)) = w(inedge2(s)))‖ (w(inedge1(l)) = w(inedge2(s)) && w(inedge2(l)) = w(inedge1(s)))) doreturn Check Start Nodes(inedge1(l), inedge1(s))elsereturn FALSEend ifendCheck Zero WeightInput: w(inedge1(l)), w(inedge2(l))Output: TRUE if there is an zero weight edge of l and Main Map returns TRUE,FALSE otherwisebeginif pred1(l) = l0 doif w(inedge1(l) = 0) return Main Map(s, pred1(l))else if w(inedge2(l) = 0) return Main Map(s, pred2(l))else return FALSEelsereturn FALSEend ifend694Sometimes there is more than one node in L that can bematched to a node in S. In order to minimize the latency of thestructure when implemented, our algorithm selects the l thathas shortest unweighted path from the source l0 to l. Graphmerging is terminated when all graphs have been processed.III. IMPLEMENTATION RESULTSThe area results for a Xilinx Virtex II [8] implementation arecompared with a standard approach using ROMs and generalmultipliers. Experimental problems of sizes between 3 × 3and 3 × 40, and with coefficients of 4, 5 and 6 bits arepresented in this paper. Although larger problem sizes caneasily be solved, this size is appropriate for comparison withthe optimal approach in [4]. It should be noted that savingsover the ROM/multiply implementation grow with the problemsize, and the area cross-over increases with bit size, as seenfrom Fig. 6. The results collected show area reductions ofup to 37% over the ROM/multiply implementation, but largerproblems will result in larger savings. Over the set of resultsthat can also be addressed by the optimal approach in [4],the heuristic area is between 25% and 79% greater than theoptimal value. This loss in area performance is because thestructure of the MCM graphs is fixed, without reference tocoefficient values in other time slots.5 10 15 20 25 30 35 400100200300400500600700800Area (slices)TxC problem size (number of C)ROM&MUL : 4 bitsHR              : 4 bitsROM&MUL : 5 bitsHR              : 5 bitsROM&MUL : 6 bitsHR              : 6 bitsFig. 6. Average area versus the problem size.The execution time of small 4-bit problems of the proposedprocedure to the optimal ILP from [4] is shown in Table I.For the biggest problem (3 × 3) that can be reasonablycomputed using ILP, it takes 61:34 hrs/mins, whereas theproposed approach uses 2.84 secs. This reduction in timeallows the proposed procedure to be embedded within a high-level synthesis flow.IV. CONCLUSIONThe work presented in this paper can be considered as anextension of [4] which a novel heuristic algorithm has beenproposed. It is based on merging graphs which involves partialmapping directed acyclic graphs representing multiple constantmultiplication obtained from each set of time-step coefficient.TABLE IVARIATION OF EXECUTION TIME FOR HEURISTIC AND ILP APPROACHThe upper figure is heuristic result and the lower figure is ILP result(in hrs:mins:secs)Problem Size C1 2 31 00:00:1.33,00:00:0.4600:00:1.40,00:00:0.5400:00:1.39,00:00:0.97T 2 00:00:1.96,00:00:5.4700:00:2.04,00:00:11.2300:00:2.04,06:00:33.523 00:00:2.70,00:01:20.7400:00:2.73,01:52:19.4900:00:2.84,61:34:48.30This paper seeks to provide a framework for future researchon the problem of multiple restricted multiplication for FPGAimplementation. There are many ways in which the heuristicapproach presented in this paper could be taken forward.The algorithm for the MRM problem on which we haveconcentrated has dealt with the operation of addition. It willbe simple in the future work to incorporate subtraction intoour algorithm. Indeed, each node of MRM graph could be dif-ferent operators, for instance, adder-multiplexer (in the case ofthis paper), adder-subtractor and subtractor-multiplexer. Futureresearch could also develop FPGA hardware implementationfor the different types of node. Some interesting steps in thisdirection have recently been made by Turner [11]. Since delayis not explicitly targeted, it may be useful in incorporatingsome function to improve the path delay.REFERENCES[1] B. Parhami, Computer Arithmetic: Algorithms and Hardware Designs.New York: Oxford University Press, 2000.[2] M. Potkonjak, M. B. Srivastava, and A. P. Chandrakasan, “Multipleconstant multiplications: efficient and versatile framework and algo-rithms for exploring common subexpression elimination,” IEEE Trans.on Computer-Aided Design of Integrated Circuits and Systems, vol. 15,pp. 151–165, February 1996.[3] M. Chen, J. Y. Jou, and H. M. Lin, “An efficient algorithm for themultiple constant multiplication problem,” in Proc. Int’l Symp. VLSITechnology, Systems, and Applications, 1999, pp. 119–122.[4] N. Sidahao, G. A. Constantinides, and P. Y. K. Cheung, “Multiple re-stricted multiplication,” in Proc. 14th Int’l Conf. on Field ProgrammableLogic and Application. FPL’04, 2004, pp. 374–383.[5] K. K. Parhi, VLSI Digital Signal Processing Systems: Design andImplementation. New York: John Wiley & Sons, 1999.[6] G. Corbaz, J. Duprat, B. Hochet, and J.-M. Muller, “Implementation ofa VLSI polynomial evaluator for real-time applications,” in Proc. Int’lConf. Application Specific Array Processors, 1991, pp. 13–24.[7] J. Villalba, G. Bandera, M. A. Gonzalez, J. Hormigo, and E. L.Zapata, “Polynomial evaluation on multimedia processors,” in Proc. Int’lConf. Application-specific Systems, Architectures and Processors (ASAP2002), San Jose, California, 2002.[8] Xilinx, Inc., “Xilinx Documentation and Literature,”http://www.xilinx.com/literature; accessed 25 September 2004.[9] A. G. Dempster and Macleod M. D., “Constant integer multiplicationusing minimum adders,” in IEE Proc. Circuits, Devices and Systems,vol. 141, October 1994, pp. 407–413.[10] G. Valiente, Algorithms on Trees and Graphs. Berlin: Springer-Verlag,2002.[11] R. H. Turner, “Functionally diverse programmable logic implementa-tions of digital signal processing algorithms,” Ph.D. dissertation, Queen’sUniversity of Belfast, August 2002.695

A Heuristic Approach for Multiple Restricted Multiplication

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A heuristic approach for multiple restricted multiplication

A heuristic approach for multiple restricted multiplication

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