In this paper we will present various hardware architecture designs for
implementing the SIMON 64/128 block cipher as a cryptographic component
offering encryption, decryption and self-contained key-scheduling capabilities
and discuss the issues and design options we encountered and the tradeoffs we
made in implementing them. Finally, we will present the results of our hardware
architectures' implementation performances on the Xilinx Spartan-6 FPGA series.Comment: 20 page