Efficient Sorting Architecture for Fast Simplified SC List Polar Decoder

Abstract

학위논문(석사)--아주대학교 일반대학원 :전자공학과,2022. 2I. Introduction 1 II. Preliminaries 4 A. SC and SCL Decoding 4 B. Path Metric 5 C. FSSC Decoding 6 D. FSSCL Decoding 6 III. Proposed Path Selection Method 9 A. Candidate Paths Selection Analysis 9 B. Proposed Metric Sorting Network 10 C. Complexity Analysis 13 IV. Simulation Results and Comparisons 14 A. Error Correction Performances 14 B. Comparisons of Complexities 14 V. Conclusions 16 Reference 17MasterThe successive cancellation (SC) decoding algorithm of polar codes shows worse error correction performances than other codes and suffers from a long latency. The SC list (SCL) and fast simplified SC (FSSC) decoding algorithms have been proposed to improve the drawbacks. In addition, the FSSC list (FSSCL) decoding has been proposed as the state-of-the-art decoding algorithm for polar codes. However, the metric sorter of the SCL decoder expands when the list size L increases and dominantly determines the critical path of the decoder. As a result, the metric sorter of the FSSCL decoder expands drastically because the FSSCL algorithm decodes multiple bits at once. To solve this problem, this paper proposes a path selection method for reducing the number of candidate paths. We analyze the cumulative result of L candidate paths selection from L2 and eliminate the unnecessary candidate paths. Finally, we simplify the bitonic sorter for the FSSCL decoder. The number of inputs is reduced by 50%, and the error correction performance is degraded less than 0.1dB on frame error rate (FER) 10-3 in L=4 and 8. The proposed sorter has up to 40% lower compare-and-swap unit (CASU) stages and up to 67% lower CASUs compared to other sorters in L=4