The urge of inventing a new low power consuming device for the post CMOS future technology has drawn the attention of the researchers on Single Electron Transistor [SET]. The two main virtues, ultra low power consumption [1] and ultra small dimension of SET [12, 13] have stimulated the researchers to consider it as a possible alternative. In our past paper [1] we have designed and simulated some basic gates. In this paper we have designed and simulated hybrid SET-CMOS based counter circuits, shift register to show that the hybrid SET-MOS based circuits consumes the lesser power than MOS based circuits. All the simulation were done and verified in Tanner environment using the MIB model for SET and the BSIM4.6.1 model for MOSFET.
When you are citing the document, use the following link http://essuir.sumdu.edu.ua/handle/123456789/3565

Jana, Anindya

Jana, Biswabandhu

Sarkar, Subir Kumar

Sing, Jamuna Kanta

SocioEconomic Challenges Journal (Sumy State University)

JOURNAL OF NANO- AND ELECTRONIC PHYSICS ЖУРНАЛ НАНО- ТА ЕЛЕКТРОННОЇ ФІЗИКИ 
Vol. 5 No 3, 03057(6pp) (2013) Том 5 № 3, 03057(6cc) (2013) 
 
 
2077-6772/2013/5(3)03057(6) 03057-1  2013 Sumy State University 
A Comparative Performance Study of Hybrid SET-CMOS Based Logic Circuits  
for the Estimation of Robustness 
 
Biswabandhu Jana1, Anindya Jana1, Jamuna Kanta Sing2, Subir Kumar Sarkar1 
 
1 Department of Electronics and Telecommunication Engineering, Jadavpur University  
2 Department of Computer Science and Engineering, Jadavpur University 
 
 (Received 15 February 2013; revised manuscript received 14 October 2013; published online 17 October 2013) 
 
The urge of inventing a new low power consuming device for the post CMOS future technology has 
drawn the attention of the researchers on Single Electron Transistor [SET]. The two main virtues, ultra 
low power consumption [1] and ultra small dimension of SET [12, 13] have stimulated the researchers to 
consider it as a possible alternative. In our past paper [1] we have designed and simulated some basic 
gates. In this paper we have designed and simulated hybrid SET-CMOS based counter circuits, shift regis-
ter to show that the hybrid SET-MOS based circuits consumes the lesser power than MOS based circuits. 
All the simulation were done and verified in Tanner environment using the MIB model for SET and the 
BSIM4.6.1 model for MOSFET. 
 
Keywords: Single electron transistor (SET), CMOS, Hybrid CMOS-SET circuits, MIB, Noise margin 
(NM), T-Spice. 
 
 PACS number: 73.61.Cw 
 
 
1. INTRODUCTION 
 
A promise of ultra-high integration densities and ul-
tra-low power consumption comes with a term: “Single 
Electron Transistor”. A high quality time of last few 
decades was afforded to understand the physics of this 
new promising candidate, in the era of low power VLSI 
circuits. The application of Single Electron Transistor 
(SET) is not only restricted for charge sensing applica-
tions [readout of few electron memories, readout of 
charge coupled devices] but it’s wide applications are in 
metrology for precession measurement [2]. In the post 
CMOS regime, SET is most common among all the Sin-
gle Electron Devices due to its several electrical charac-
teristics and conceptually simplicity. There are different 
numerical simulators for the precise simulation of SET, 
like SIMON [3], KOSEC [4] and MOSES [5]. These all 
models are accurate from their side, but they are not as 
useful as circuit simulation purpose and they are high 
time consuming also. Operation of Single Electron 
Transistor is based on the transfer of one by one elec-
tron, through the channel. SET has unique characteris-
tic like periodically increasing and decreasing of drain 
current with respect to gate voltage. To take the full 
advantage of this unique feature we need to analyze its 
behavior in circuits, whether the circuits working 
properly with low power consumption than before or 
not. SET has a major advantage over MOSFET i.e. low 
power consumption, along with its Nanoscale feature 
seize and unique Coulomb blockade characteristics. But 
it has some drawbacks also like low current drive, back-
ground charge effect and mainly lack of room tempera-
ture operable technology. But nowadays the drawback 
of room temperature operable technology has been over-
come. Researchers have invented room temperature 
operable SET [6]. Apart from this by overcoming the 
drawbacks of SET and MOSFET a new device draw the 
attention of the researchers: Hybrid SET-CMOS tech-
nology, which comprises of the advantages of SET and 
CMOS [7]. Fig. 1 shows a circuital representation of 
SET. In our previous work [1] we have designed some 
basic gates and showed that the concept of hybridization 
is a new possibility in low power VLSI design. 
 
 
Fig. 1 – Schematic structure of SET 
 
In the modern digital circuits and computing also, 
counters are such a device which stores and sometimes 
displays a number of times an event, happening with 
respect to a clock signal. A wide variety of classifica-
tions in counters exist. Each is different in application. 
Practically Counters count natural binary, though they 
are digital in nature. In our present paper we have de-
signed Synchronous up counter, Synchronous down 
Counter, Synchronous up down Counter, Asynchronous 
up counter, Asynchronous down counter, Asynchronous 
up down counter, Synchronous Asynchronous decade 
counter, Shift Register. We have used MIB model. All 
the circuits are verified by means of T-Spice simulation 
software. The MIB compact model for SET devices and 
BSIM 4.6.1 model for CMOS are used in our paper. 
 
2. SINGLE ELECTRON TRANSISTOR  
 
The concept of Single Electronics comes from the 
thoughts of Quantum devices, better to say, “Quantum 
Dot”. A portion of matter is called Quantum Dot, whose 
excitations are confined in three spatial dimensions. 
These types of materials have electronic properties in-
termediate between those of bulk semiconductors and 
those of discrete molecules. They were discovered at the 
beginning of the 1980s by Alexei Ekimov [8] in a glass 
matrix and by Louis E. Brus in colloidal solutions. The 
term "quantum dot" was coined by Mark Reed [9]. 
Researchers have studied quantum dots in transis-
tors, solar cells, LEDs, and diode lasers. They have also 
investigated quantum dots as agents for medical imag-
ing and hope to use them as cubits in quantum compu-
 ANINDYA JANA, ET AL. J. NANO- ELECTRON. PHYS. 5, 03057 (2013) 
 
 
03057-2 
ting. Quantum dots are one type of semiconductors 
whose electronic characteristics are closely related to 
the size and shape of the individual crystal. Generally 
band gap seize is inversely proportional to the size of 
the crystal. Again, the smaller the size of the crystal 
means, the greater the difference in energy between 
the highest valence band and the lowest conduction 
band. Therefore more energy is needed for the excita-
tion of the dot, and concurrently, more energy is re-
leased when the crystal returns to its resting state. 
 
 
 
Fig. 2 – Quantum dot  
 
2.1 Basic of Single Electronics 
 
Let we take an example of small conductor, which is 
initially electro neutral; have exactly as many electrons 
as it has protons in its crystal lattice. In this condition 
any appreciable electric field is not generated by the is-
land beyond its border and an additional electron may 
bring in due to a weak external force. Now the net 
charge is – e. The charging energy of the island is EC, 
where the total capacitance is C and EC can be calculat-
ed from [10]. 
 
 
2
C
e
E
C
  (1) 
 
When the size of the island becomes comparable 
with the de Broglie wavelength of the electron inside 
the island, energy quantization 
 
 
2 2 2
2
( )
22
N
n k
E
xxw

   (2) 
 
The electron addition energy (Ea) can be calculated 
from [10] 
 
 a C KE E E   (3) 
 
EK – quantum kinetic energy of the addition electron 
[10]; for a degenerate electron gas 
 
 
1
( )
K
F
E
g V


 (4) 
 
Where V is the island volume and ( )Fg   is the den-
sity of states on the Fermi surface. Where V is the is-
land volume and ( )Fg   is the density of states on the 
Fermi surface. 
 
 
 
2.2 Transfer of Electron through a Quantum Dot 
 
Electron transfer through a quantum dot is inter-
play of two effects: resonant tunneling effects and Cou-
lomb Blockade effect. When the Fermi energy EF in the 
source lines up with one of the energy levels in the dot 
then the resonant tunneling happens. And in very low 
temperature the energy, required to charge the junc-
tion with one elementary charge is larger than the 
thermal energy of the charge carriers. This phenome-
non is called Coulomb Blockade. 
 
3. HYBRID MOS-SET  
 
The concept of hybridization of SET with MOSFET 
was introduced to overcome the problems of SET, like, 
low current drive, lack of room temperature operable 
technology and back ground charge effects. This con-
cept was totally based on the advantages of MOSFET 
and SET. All the simulations of hybrid circuits are done 
using MIB model [11], BSIM 4.6.1 model card. 
 
4. HYBRID CMOS-SET COUNTERS 
 
4.1 Hybrid Synchronous Up Counter 
 
Fig. 3 shows the diagram of 4 bit (MOD-16) Hybrid 
synchronous up counter. Only LSB J K flipflop con-
nected to Vdd. Initially qa  qb  qc  qd  0. Flipflop 
changes its state when qa  qb  qc  qd  1, which is 
depicted in Fig. 4. 
 
 
 
Fig. 3 – A 4 bit Hybrid SET-CMOS based synchronous up 
counter 
 
4.2 Synchronous Down Counter 
 
Fig. 5 shows the diagram of 4 bit (MOD-16) Hybrid 
synchronous down counter. Initially 
qa  qb  qc  qd  1. The parallel counter counts down 
by inverted output of the J K flipflop. The output is 
reflected in Fig. 6. 
 
 A COMPARATIVE PERFORMANCE STUDY OF HYBRID SET-CMOS… J. NANO- ELECTRON. PHYS. 5, 03057 (2013) 
 
 
03057-3 
 
 
Fig. 4 – Simulation output of 4 bit hybrid synchronous up 
counter 
 
 
 
Fig. 5 – A 4 bit hybrid SET-CMOS based synchronous down 
counter  
 
4.3 Synchronous Up / Down Counter 
 
A 3 bit (MOD-8) Hybrid Synchronous Up / Down Coun-
ter (Shown in Fig. 7) use control input COUNT-UP & 
COUNT DOWN to work as a multimode counter. When 
COUNT-UP  1 & COUNT DOWN  0 it counts from 
000 to 111.The reverse action occurs with COUNT-
UP  0 & COUNT DOWN  1.This counter produces 
same output as illustrated in Fig. 4 in up counting & 
Fig. 6 in down counting operation. 
 
4.4 Asynchronous Up Counter 
 
A 4 bit Hybrid Asynchronous (Ripple or Serial) Up 
Counter shown in Fig. 8 counts from logic 0 state 
(qa  qb  qc  qd  0) to qa  qb  qc  qd  1. 
 
 
Fig. 6 – Simulation output of 4 bit hybrid synchronous down 
counter 
 
 
 
Fig. 7 – A 4 bit hybrid SET-CMOS based synchronous up 
down counter  
 
All inputs of the J K flipflops are connected to Vdd 
& clock inputs are connected to LSB flipflop. Therefore 
signal transmits through the asynchronous up counter 
in a ripple fashion. 
 
4.5 Asynchronous Down Counter 
 
A 4 bit hybrid asynchronous down counter illustrat-
ed in Fig. 10, each flipflop toggles its state according to 
the inverted output of the previous flipflop. It is decre-
mented by 1 (initially qa  qb  qc  qd  1) at each tran-
sition and reaches to zero state. 
 
 ANINDYA JANA, ET AL. J. NANO- ELECTRON. PHYS. 5, 03057 (2013) 
 
 
03057-4 
 
 
Fig. 8 – A 4 bit hybrid SET-CMOS based asynchronous up 
counter 
 
 
 
Fig. 9 – Simulation output of 4 bit hybrid asynchronous up 
counter 
 
 
 
Fig. 10 – A 4 bit hybrid SET-CMOS based asynchronous down 
counter  
 
 
 
Fig. 11 – Simulation output of 4 bit hybrid asynchronous 
down counter 
 
4.6 Hybrid Asynchronous Up / Down Counter 
 
A 4 bit hybrid asynchronous up / down counter as 
described in Fig. 12 switch to multimode counter by 
using control input COUNT-UP & COUNT DOWN. It 
cannot count when both control inputs are 1 or 0.It 
produces same output as shown in Fig. 9 (up mode) & 
Fig. 11 (down mode). 
 
4.7 Hybrid Synchronous / Asynchronous De-
cade Counter 
 
Hybrid Synchronous/Asynchronous decade Counter, 
shown in Fig. 13, made by combining  Synchronous & 
Asynchronous Counter, provides a comprise between 
the speed of Synchronous counter & simplicity of Asyn-
chronous Counter. At the 10th pulse flip-flop will toggle 
& bring the counter back to 0000 state from 1001 state. 
 
Table 1 – Comparison of average of power 
 
Sl 
No. 
Name of the 
Circuit 
Power Con-
sumed Us-
ing Hybrid 
SET-CMOS 
Model 
Power Con-
sumed Us-
ing 
MOSFET 
Model 
1 Synchronous up 
counter 
1.319269e-
010 watts 
2.115174e-
009 watts 
2 Synchronous 
down counter 
1.080815e-
010 watts 
2.073577e-
009 watts 
3 Synchronous 
up / down 
counter 
   1.189205e-
010 watts 
2.585096e-
009 watts 
4 Asynchronous 
up counter 
1.928327e-
010 watts 
1.355511e-
008 watts 
5 Asynchronous 
down counter 
1.933616e-
010 watts 
1.356138e-
008 watts 
6 Asynchronous 
up / down 
counter 
1.916439e-
010 watts 
9.035318e-
009 watts 
7 Synchronous 
asynchronous 
decade counter 
1.325760e-
010 watts 
7.514414e-
009 watts 
8 Hybrid shift 
register 
5.890781e-
010 watts 
3.100656e-
009 watts 
 
 
 A COMPARATIVE PERFORMANCE STUDY OF HYBRID SET-CMOS… J. NANO- ELECTRON. PHYS. 5, 03057 (2013) 
 
 
03057-5 
 
 
Fig. 12 – A 4 bit hybrid SET-CMOS based asynchronous up 
down counter 
 
4.8 Hybrid Shift Register 
 
Fig. 16 reflects the simulation output of hybrid 
SET-CMOS based 4 bit shift register circuit, which can 
shifts binary information in both direction or in same 
depending on the clock input. 
 
5. RESULTS & DISCUSSION 
 
We have simulated the above circuits using 
BSIM 4.6.1 and MIB model in tanner environment. The 
parameters used for the simulation are the room tem-
perature parameters [1, 14, and 15], which are reflect-
ed in Table 1. 
 
6. CONCLUSION 
 
Employing a uniform interval of clock pulse, counter 
carries out a predetermined sequence of states. In this 
section we have projected the conception of hybrid SET 
CMOS architecture by designing counter. Also this mod-
ule portrays the comparison of power consumption in 
hybrid SET-CMOS model & conventional MOS model. 
Thus we have shown the novelty and robustness of our 
model. The low power consumption of hybrid model 
attracts the attention of the entire VLSI designer. As 
the operating temperature becomes sub ambient re-
gime, overall performance (switching speed, mobility, 
power dissipation) will be better. Here all the SET-
CMOS design & simulation are done in room tempera-
ture so that it exhibits their full functionalities. 
 
 
 
Fig. 13 – A 4 bit hybrid SET-CMOS based synchronous-
asynchronous decade counter 
 
 
 
Fig. 14 – Simulation output of a 4 bit hybrid synchronous-
asynchronous decade counter 
 
ACKNOWLEDGEMENT 
 
Anindya Jana thankfully acknowledges the finan-
cial support obtained from State Research Fellowship, 
Jadavpur University, Kolkata. 
Subir Kumar Sarkar thankfully acknowledges the financial sup-
port obtained in the form of fellowship from UGC UPE PHASE 
–II, “Devices and Systems” 
 ANINDYA JANA, ET AL. J. NANO- ELECTRON. PHYS. 5, 03057 (2013) 
 
 
03057-6 
 
 
Fig. 15 – A 4 bit hybrid SET-CMOS based shift register 
 
 
 
Fig. 16 – Simulation output of 4 bit hybrid shift register 
 
 
 
Fig. 17 – Comparison of power consumption hybrid model & 
MOS model 
.
 
REFERENCES 
 
1. Anindya Jana, N. Basant Singh, Jamuna Kanta Sing, 
Subir Kumar Sarkar, Microelectron. Reliab. 53, 592 
(2013). 
2. K.K. Likharev, Proc. IEEE  87, 606 (1999). 
3. C. Wasshuber, H. Kosina, S. Selberherr, IEEE T. Comput. 
Aid D. 16, 937 (1997). 
4. Y.S. Yu, J.H. Oh, S.W. Hawang, D. Ahn, In Proceedings of 
Asia Pacific Workshop Fundamental Application Advanced 
Semiconductor Device 100, 85 (2000). 
5. R.H. Chen, A.N. Korotkov, K.K. Likharev, Proc. Dev. Res. 
Conference 44 (1995). 
6. K. Matsumoto, Appl. Phys. Lett. 68, 34 (1996). 
7. Aaron A. Prager, Hubert C. George, Alexei O. Orlov,  
Gregory L. Snider, J. Vac. Sci. Technol. B 29, 041004 
(2011). 
8. A.I. Ekimov, A.A. Onushchenko, JETP Lett. 34, 345 (1981). 
9. M.A. Reed, J.N. Randall, R.J. Aggarwal, R.J. Matyi, 
T.M. Moore, A.E. Wetsel, Phys. Rev. Lett. 60, 535 (1988). 
10. K.K. Likharev, Proc. IEEE, 87, 606 (1999). 
11. Santanu Mahapatra, Adrian Mihai Ionescu, Artech House, 
Inc.,ISBN:1596930691,2006. 
12. Z.K. Durrani, A.C. Irvine, H. Ahmed, IEEE T. Electron 
Dev. 47, 2334 (2000). 
13. D.L. Klein, P.L. McEuen, J.E.B. Katari, R. Roth, 
A.P. Alivisatos, Appl. Phys. Lett. 68, 2574 (1996). 
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Y. Takahashi, et al., Nano Lett. 11,1591 (2011). 
 


A Comparative Performance Study of Hybrid SET-CMOS Based Logic Circuits for the Estimation of Robustness

Electronic Sumy State University Institutional Repository

JOURNAL OF NANO- AND ELECTRONIC PHYSICS ЖУРНАЛ НАНО- ТА ЕЛЕКТРОННОЇ ФІЗИКИ Vol. 5 No 3, 03057(6pp) (2013) Том 5 № 3, 03057(6cc) (2013)   2077-6772/2013/5(3)03057(6) 03057-1  2013 Sumy State University A Comparative Performance Study of Hybrid SET-CMOS Based Logic Circuits  for the Estimation of Robustness  Biswabandhu Jana1, Anindya Jana1, Jamuna Kanta Sing2, Subir Kumar Sarkar1  1 Department of Electronics and Telecommunication Engineering, Jadavpur University  2 Department of Computer Science and Engineering, Jadavpur University   (Received 15 February 2013; revised manuscript received 14 October 2013; published online 17 October 2013)  The urge of inventing a new low power consuming device for the post CMOS future technology has drawn the attention of the researchers on Single Electron Transistor [SET]. The two main virtues, ultra low power consumption [1] and ultra small dimension of SET [12, 13] have stimulated the researchers to consider it as a possible alternative. In our past paper [1] we have designed and simulated some basic gates. In this paper we have designed and simulated hybrid SET-CMOS based counter circuits, shift regis-ter to show that the hybrid SET-MOS based circuits consumes the lesser power than MOS based circuits. All the simulation were done and verified in Tanner environment using the MIB model for SET and the BSIM4.6.1 model for MOSFET.  Keywords: Single electron transistor (SET), CMOS, Hybrid CMOS-SET circuits, MIB, Noise margin (NM), T-Spice.   PACS number: 73.61.Cw   1. INTRODUCTION  A promise of ultra-high integration densities and ul-tra-low power consumption comes with a term: “Single Electron Transistor”. A high quality time of last few decades was afforded to understand the physics of this new promising candidate, in the era of low power VLSI circuits. The application of Single Electron Transistor (SET) is not only restricted for charge sensing applica-tions [readout of few electron memories, readout of charge coupled devices] but it’s wide applications are in metrology for precession measurement [2]. In the post CMOS regime, SET is most common among all the Sin-gle Electron Devices due to its several electrical charac-teristics and conceptually simplicity. There are different numerical simulators for the precise simulation of SET, like SIMON [3], KOSEC [4] and MOSES [5]. These all models are accurate from their side, but they are not as useful as circuit simulation purpose and they are high time consuming also. Operation of Single Electron Transistor is based on the transfer of one by one elec-tron, through the channel. SET has unique characteris-tic like periodically increasing and decreasing of drain current with respect to gate voltage. To take the full advantage of this unique feature we need to analyze its behavior in circuits, whether the circuits working properly with low power consumption than before or not. SET has a major advantage over MOSFET i.e. low power consumption, along with its Nanoscale feature seize and unique Coulomb blockade characteristics. But it has some drawbacks also like low current drive, back-ground charge effect and mainly lack of room tempera-ture operable technology. But nowadays the drawback of room temperature operable technology has been over-come. Researchers have invented room temperature operable SET [6]. Apart from this by overcoming the drawbacks of SET and MOSFET a new device draw the attention of the researchers: Hybrid SET-CMOS tech-nology, which comprises of the advantages of SET and CMOS [7]. Fig. 1 shows a circuital representation of SET. In our previous work [1] we have designed some basic gates and showed that the concept of hybridization is a new possibility in low power VLSI design.   Fig. 1 – Schematic structure of SET  In the modern digital circuits and computing also, counters are such a device which stores and sometimes displays a number of times an event, happening with respect to a clock signal. A wide variety of classifica-tions in counters exist. Each is different in application. Practically Counters count natural binary, though they are digital in nature. In our present paper we have de-signed Synchronous up counter, Synchronous down Counter, Synchronous up down Counter, Asynchronous up counter, Asynchronous down counter, Asynchronous up down counter, Synchronous Asynchronous decade counter, Shift Register. We have used MIB model. All the circuits are verified by means of T-Spice simulation software. The MIB compact model for SET devices and BSIM 4.6.1 model for CMOS are used in our paper.  2. SINGLE ELECTRON TRANSISTOR   The concept of Single Electronics comes from the thoughts of Quantum devices, better to say, “Quantum Dot”. A portion of matter is called Quantum Dot, whose excitations are confined in three spatial dimensions. These types of materials have electronic properties in-termediate between those of bulk semiconductors and those of discrete molecules. They were discovered at the beginning of the 1980s by Alexei Ekimov [8] in a glass matrix and by Louis E. Brus in colloidal solutions. The term "quantum dot" was coined by Mark Reed [9]. Researchers have studied quantum dots in transis-tors, solar cells, LEDs, and diode lasers. They have also investigated quantum dots as agents for medical imag-ing and hope to use them as cubits in quantum compu- ANINDYA JANA, ET AL. J. NANO- ELECTRON. PHYS. 5, 03057 (2013)   03057-2 ting. Quantum dots are one type of semiconductors whose electronic characteristics are closely related to the size and shape of the individual crystal. Generally band gap seize is inversely proportional to the size of the crystal. Again, the smaller the size of the crystal means, the greater the difference in energy between the highest valence band and the lowest conduction band. Therefore more energy is needed for the excita-tion of the dot, and concurrently, more energy is re-leased when the crystal returns to its resting state.    Fig. 2 – Quantum dot   2.1 Basic of Single Electronics  Let we take an example of small conductor, which is initially electro neutral; have exactly as many electrons as it has protons in its crystal lattice. In this condition any appreciable electric field is not generated by the is-land beyond its border and an additional electron may bring in due to a weak external force. Now the net charge is – e. The charging energy of the island is EC, where the total capacitance is C and EC can be calculat-ed from [10].   2CeEC  (1)  When the size of the island becomes comparable with the de Broglie wavelength of the electron inside the island, energy quantization   2 2 22( )22Nn kExxw   (2)  The electron addition energy (Ea) can be calculated from [10]   a C KE E E   (3)  EK – quantum kinetic energy of the addition electron [10]; for a degenerate electron gas   1( )KFEg V (4)  Where V is the island volume and ( )Fg   is the den-sity of states on the Fermi surface. Where V is the is-land volume and ( )Fg   is the density of states on the Fermi surface.    2.2 Transfer of Electron through a Quantum Dot  Electron transfer through a quantum dot is inter-play of two effects: resonant tunneling effects and Cou-lomb Blockade effect. When the Fermi energy EF in the source lines up with one of the energy levels in the dot then the resonant tunneling happens. And in very low temperature the energy, required to charge the junc-tion with one elementary charge is larger than the thermal energy of the charge carriers. This phenome-non is called Coulomb Blockade.  3. HYBRID MOS-SET   The concept of hybridization of SET with MOSFET was introduced to overcome the problems of SET, like, low current drive, lack of room temperature operable technology and back ground charge effects. This con-cept was totally based on the advantages of MOSFET and SET. All the simulations of hybrid circuits are done using MIB model [11], BSIM 4.6.1 model card.  4. HYBRID CMOS-SET COUNTERS  4.1 Hybrid Synchronous Up Counter  Fig. 3 shows the diagram of 4 bit (MOD-16) Hybrid synchronous up counter. Only LSB J K flipflop con-nected to Vdd. Initially qa  qb  qc  qd  0. Flipflop changes its state when qa  qb  qc  qd  1, which is depicted in Fig. 4.    Fig. 3 – A 4 bit Hybrid SET-CMOS based synchronous up counter  4.2 Synchronous Down Counter  Fig. 5 shows the diagram of 4 bit (MOD-16) Hybrid synchronous down counter. Initially qa  qb  qc  qd  1. The parallel counter counts down by inverted output of the J K flipflop. The output is reflected in Fig. 6.   A COMPARATIVE PERFORMANCE STUDY OF HYBRID SET-CMOS… J. NANO- ELECTRON. PHYS. 5, 03057 (2013)   03057-3   Fig. 4 – Simulation output of 4 bit hybrid synchronous up counter    Fig. 5 – A 4 bit hybrid SET-CMOS based synchronous down counter   4.3 Synchronous Up / Down Counter  A 3 bit (MOD-8) Hybrid Synchronous Up / Down Coun-ter (Shown in Fig. 7) use control input COUNT-UP & COUNT DOWN to work as a multimode counter. When COUNT-UP  1 & COUNT DOWN  0 it counts from 000 to 111.The reverse action occurs with COUNT-UP  0 & COUNT DOWN  1.This counter produces same output as illustrated in Fig. 4 in up counting & Fig. 6 in down counting operation.  4.4 Asynchronous Up Counter  A 4 bit Hybrid Asynchronous (Ripple or Serial) Up Counter shown in Fig. 8 counts from logic 0 state (qa  qb  qc  qd  0) to qa  qb  qc  qd  1.   Fig. 6 – Simulation output of 4 bit hybrid synchronous down counter    Fig. 7 – A 4 bit hybrid SET-CMOS based synchronous up down counter   All inputs of the J K flipflops are connected to Vdd & clock inputs are connected to LSB flipflop. Therefore signal transmits through the asynchronous up counter in a ripple fashion.  4.5 Asynchronous Down Counter  A 4 bit hybrid asynchronous down counter illustrat-ed in Fig. 10, each flipflop toggles its state according to the inverted output of the previous flipflop. It is decre-mented by 1 (initially qa  qb  qc  qd  1) at each tran-sition and reaches to zero state.   ANINDYA JANA, ET AL. J. NANO- ELECTRON. PHYS. 5, 03057 (2013)   03057-4   Fig. 8 – A 4 bit hybrid SET-CMOS based asynchronous up counter    Fig. 9 – Simulation output of 4 bit hybrid asynchronous up counter    Fig. 10 – A 4 bit hybrid SET-CMOS based asynchronous down counter     Fig. 11 – Simulation output of 4 bit hybrid asynchronous down counter  4.6 Hybrid Asynchronous Up / Down Counter  A 4 bit hybrid asynchronous up / down counter as described in Fig. 12 switch to multimode counter by using control input COUNT-UP & COUNT DOWN. It cannot count when both control inputs are 1 or 0.It produces same output as shown in Fig. 9 (up mode) & Fig. 11 (down mode).  4.7 Hybrid Synchronous / Asynchronous De-cade Counter  Hybrid Synchronous/Asynchronous decade Counter, shown in Fig. 13, made by combining  Synchronous & Asynchronous Counter, provides a comprise between the speed of Synchronous counter & simplicity of Asyn-chronous Counter. At the 10th pulse flip-flop will toggle & bring the counter back to 0000 state from 1001 state.  Table 1 – Comparison of average of power  Sl No. Name of the Circuit Power Con-sumed Us-ing Hybrid SET-CMOS Model Power Con-sumed Us-ing MOSFET Model 1 Synchronous up counter 1.319269e-010 watts 2.115174e-009 watts 2 Synchronous down counter 1.080815e-010 watts 2.073577e-009 watts 3 Synchronous up / down counter    1.189205e-010 watts 2.585096e-009 watts 4 Asynchronous up counter 1.928327e-010 watts 1.355511e-008 watts 5 Asynchronous down counter 1.933616e-010 watts 1.356138e-008 watts 6 Asynchronous up / down counter 1.916439e-010 watts 9.035318e-009 watts 7 Synchronous asynchronous decade counter 1.325760e-010 watts 7.514414e-009 watts 8 Hybrid shift register 5.890781e-010 watts 3.100656e-009 watts    A COMPARATIVE PERFORMANCE STUDY OF HYBRID SET-CMOS… J. NANO- ELECTRON. PHYS. 5, 03057 (2013)   03057-5   Fig. 12 – A 4 bit hybrid SET-CMOS based asynchronous up down counter  4.8 Hybrid Shift Register  Fig. 16 reflects the simulation output of hybrid SET-CMOS based 4 bit shift register circuit, which can shifts binary information in both direction or in same depending on the clock input.  5. RESULTS & DISCUSSION  We have simulated the above circuits using BSIM 4.6.1 and MIB model in tanner environment. The parameters used for the simulation are the room tem-perature parameters [1, 14, and 15], which are reflect-ed in Table 1.  6. CONCLUSION  Employing a uniform interval of clock pulse, counter carries out a predetermined sequence of states. In this section we have projected the conception of hybrid SET CMOS architecture by designing counter. Also this mod-ule portrays the comparison of power consumption in hybrid SET-CMOS model & conventional MOS model. Thus we have shown the novelty and robustness of our model. The low power consumption of hybrid model attracts the attention of the entire VLSI designer. As the operating temperature becomes sub ambient re-gime, overall performance (switching speed, mobility, power dissipation) will be better. Here all the SET-CMOS design & simulation are done in room tempera-ture so that it exhibits their full functionalities.    Fig. 13 – A 4 bit hybrid SET-CMOS based synchronous-asynchronous decade counter    Fig. 14 – Simulation output of a 4 bit hybrid synchronous-asynchronous decade counter  ACKNOWLEDGEMENT  Anindya Jana thankfully acknowledges the finan-cial support obtained from State Research Fellowship, Jadavpur University, Kolkata. Subir Kumar Sarkar thankfully acknowledges the financial sup-port obtained in the form of fellowship from UGC UPE PHASE –II, “Devices and Systems”  ANINDYA JANA, ET AL. J. NANO- ELECTRON. PHYS. 5, 03057 (2013)   03057-6   Fig. 15 – A 4 bit hybrid SET-CMOS based shift register    Fig. 16 – Simulation output of 4 bit hybrid shift register    Fig. 17 – Comparison of power consumption hybrid model & MOS model . REFERENCES  1. Anindya Jana, N. Basant Singh, Jamuna Kanta Sing, Subir Kumar Sarkar, Microelectron. Reliab. 53, 592 (2013). 2. K.K. Likharev, Proc. IEEE  87, 606 (1999). 3. C. Wasshuber, H. Kosina, S. Selberherr, IEEE T. Comput. Aid D. 16, 937 (1997). 4. Y.S. Yu, J.H. Oh, S.W. Hawang, D. Ahn, In Proceedings of Asia Paciﬁc Workshop Fundamental Application Advanced Semiconductor Device 100, 85 (2000). 5. R.H. Chen, A.N. Korotkov, K.K. Likharev, Proc. Dev. Res. Conference 44 (1995). 6. K. Matsumoto, Appl. Phys. Lett. 68, 34 (1996). 7. Aaron A. Prager, Hubert C. George, Alexei O. Orlov,  Gregory L. Snider, J. Vac. Sci. Technol. B 29, 041004 (2011). 8. A.I. Ekimov, A.A. Onushchenko, JETP Lett. 34, 345 (1981). 9. M.A. Reed, J.N. Randall, R.J. Aggarwal, R.J. Matyi, T.M. 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A Comparative Performance Study of Hybrid SET-CMOS Based Logic Circuits for the Estimation of Robustness

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