Popov, V

Riege, H

Schütt, J

Van Staa, R

CERN Document Server

THE HERA-B HIGH-PT LEVEL-0 TRIGGER LOGIC ELECTRONICSH.Riege,  J.Schütt, R.van Staa, II.Institut für Experimentalphysik, Universität Hamburg , GermanyV.Popov, Institute for Theoretical and Experimental Physics, Moscow, RussiaAbstractThe high-pt trigger has been proposed for broaden-ing of the HERA-B physics program. A dedicated logicsystem is needed to select events out of a data streamwith typical rate of 1012 hits/sec. The paper describesthe trigger logic electronics system and data processingwhich provide necessary speed and flexibility for thelevel-0 trigger selection criteria.1.  INTRODUCTIONOne of the main goals of the HERA-B experiment isthe measurement of the asymmetry in B → J/ψK0sdecay mode. The high-pt ‘hadron’ trigger considerablybroadens the HERA-B physics program. It provides theexperiment with the ability to measure CKM unitarytriangle angles α and γ by detection of the  B → π+ π-and     B → K π decays [1], the expected numbers ofreconstructed events are 500 and 750 per year corre-spondingly. The high-pt trigger allows either to meas-ure the Bs mixing frequency in Bs → Dsh mode, wherethe expected number of reconstructed events is about400 per year.The high-pt Level-0 trigger (pretrigger) selects can-didates for particles with large transverse momentumand provides the First Level Trigger (FLT) with initialinformation to start the track finding process. It is ableto detect and encode approximately 108 track candi-dates out of 1012 possible combinations per seconds.A description of the main components of the High-ptpretrigger system can be found in [2]. This papermainly describes the logic electronics.2.  PRETRIGGER HARDWAREIMPLEMENTATIONThe high-pt  pretrigger is organised using approxi-mately 19000 pads of different size distributed amongthree layers of chambers located in the magnet. Thereis a projectivity betweenposition and size of corre-spondent pads in three lay-ers with respect to the ver-tex position. Pad sizes arevarying in correspondencewith their distance from thebeam.For the high-pt  pretriggerthe following track selection algorithm has been im-plemented (s. fig.1): each pad of the first chamber layer(PT1) maps to up to five adjacent pads in the secondlayer PT2, and each pad of PT2 maps to two adjacentpads of the third layer PT3. The tracks with largetransverse momentum produce signals in projective oradjacent pads of three chamber layers.The pretrigger logic electronics has sectional struc-ture and consists of three types of boards, the LinkBoard, the Pretrigger Board and the Message Generator(Master Card). Each section is covered by one MasterCard and up to 8 Pretrigger Boards, while each Pre-trigger Board is connected to 6 Link Boards.The Link Board is located near the detector and pro-vides via optical fibres the fast data transfer to the maintrigger Logic.A Pretrigger Board receives the data of two com-plete pad rows of all three detector layers. Data whichmatch to the trigger algorithm are encoded and trans-mitted to the Message Generator on a dedicated bus.The Message Generator acquires data pattern from agroup of connected Pretrigger Boards, transforms themby means of a look-up table into some messages,which are sent to the Track Finding Unit (TFU) of theHERA-B Level-1 Trigger system.3. LINK BOARDFig.2 shows the block diagram of one link channelon the Link Board. It transmits the digital data of twohalf chamber rows during one bunch crossing intervalof 96 nsec. Therefore at first the incoming data have tobe stored in registers. With a period of 48 nsec theregister outputs are multiplexed to two Autobahntransmitters (Motorola MC100SX1451), which are 32-bit parallel-to-serial transceivers with an effective datarate of 800 Mbit/sec. On the first transfer channel  30pad bits are sent together with one Bunch Number bitand a Cycle Bit CB, which distinguishes between thetwo detector rows. The second transmitter sends theFig.1: Trigger RoadsPT1         PT2         PT3Reg.Reg.Reg.Reg.3030nnRow mRow mRow m+1Row m+1Auto-bahn  Opt.  LinkAuto-bahnOpt.  Link30nCBCB1BNBN8Fig.2: Block Diagram of Link Channelremaining pad bits, the complete Bunch Number BNand again the Cycle Bit.The serial Autobahn output is connected to an opti-cal transmitter [3], which sends the data to the Pretrig-ger Board over a distance of about 45 m.One Link Board contains three link channels. It isoperating synchronously with the Bunch Clock. It hasbeen designed as piggy back on the Front End DriverCard, which collects the pad bits for data acquisition.4. PRETRIGGER BOARDThe Pretrigger Board PTB searches for coincidencepattern as trigger candidates and combines for eachtrigger road the involved pads to data packages, whichare sent to the Message Generator. Fig.3 shows a blockdiagram of its main components.4.1 Data Transfer from the DetectorDuring one HERA bunch crossing interval the Pre-trigger Board has to receive and process the completepad information of two detector rows of all threeplanes. Since the maximum number of pads per row is96, every 48 nsec in total 278 detector bits togetherwith redundant bunch number information are sent tothe PTB on 12 transfer channels. Each channel consistof a pair of Autobahn transceivers (Motorola,MC100SX1451) and an optical link between theirserial ports [3].4.2 Coincidence LogicThe Coincidence Logic is able to combine each padof the first detector layer with up to 5 pads of the sec-ond and up to 6 pads of the third layer. Fig.1 shows anexample of a possible Trigger Road structure. TheLogic has been designed as a 3-stage pipeline with aclock period of 48 nsec. With the first strobe a data setof 3*96 bits is stored in the Input Register. For eachpad of the first layer, which is found to be a startingpoint of a trigger road, a Road Starting Flag RSF is set.The resulting RSF pattern together with the pad infor-mation of the other layers then is stored with the nextstrobe. Only if at least one RSF has been detected, aRoad Flag (R-Flg) is set and the complete data set iswritten to the Event FIFO with the third strobe (ZeroSuppression).The Coincidence Logic has been implemented bymeans of 6 large CPLD’s (Vantis, MACH466), whichare in-system programmable. So the coincidence algo-rithm easily can be modified by reprogramming thefirmware. A VME access to the Coincidence Logic isprovided for a Mask Register, which allows to disableeach input bit individually, and for a Test Register,which in Test Mode emulates the detector input.4.3 Bunch Number ComparisonOn each of the 12 transfer channels to the PTB someBunch Number bits are transmitted. Since these are theonly predictable information, they are used to  monitorthe reliability of data transfer by comparing 66 bits inreal time. If a comparison fault is detected, an errorflag is set, and an interrupt can be generated.4.4 Event FIFOThe Event FIFO stores data sets consisting of a 96bit RSF pattern, two 96 bit pad pattern of the secondand third chamber layer, the 8 bit Bunch Number andthe Cycle Bit. It decouples the system clock on theinput side, which is synchronised with the Autobahnclock and has a period of 48 nsec, from the outputsystem clock with a frequency of 25 MHz. Addition-Autobahn   ReceiverVMEVMEBunch Nr.ComparisonCoincidenceLogicInput Reg.Mask Reg.Test Reg.Event FIFO512*297 BitMultiplexer95:6Multiplexer96:5Encoder7 BitOutputRegisterTest FIFO512*32 Bit966696969696969969696 745697569Card272R-Flg12Fig.3: Block Diagram of  Pretrigger Boardally it acts as data buffer, because one input data setcan generate more then one output data package. TheEvent FIFO has a depth of 512 words and is built of 17chips SN74ALVC7804 (Texas Instruments).4.5 Output DataThe output system clock drives a Finite State Ma-chine controlling the output data generation, whichagain is organised as 3-stage pipeline process. In thefirst step a 7-bit Priority Encoder generates a binarycode for the actual most significant RSF bit. Then thatcode is used to address two Multipexers selecting thecorresponding up to 5 pads of the second and up to 6pads of the third layer. The resulting data together withthe 8 bit Bunch Number and the Cycle Bit are writtento the Output Register in the last step.4.6 Data Transfer to Message GeneratorSince up to 8 Pretrigger Boards have to be connectedto one Message Generator, the output data are trans-mitted on a bus. The communication protocol has beenimplemented by 8 dedicated 2-wire handshakes pro-viding fast identification of data source. The data trans-fer time is 40 nsec.4.7 Test FacilitiesIn order to be able to test the Logic of the board,there are Test Registers implemented, which cover thecomplete input range of 288 bits. The test patternstored via VME is processed in real time, and the re-sulting output data are written to a Test FIFO, whichcan be read-out by VME for comparison with the ex-pected values. The Test FIFO also is useful for moni-toring the data stream during data acquisition.4.8 Additional FeaturesThere are some other important features of the PTB,which for reasons of simplicity are not shown in theblock diagram:⇒ A Veto Logic accept Bunch Numbers distributedby the HERA-B Calorimeter in order to inhibitcertain events.⇒ A 29-bit counter monitors the number of generatedoutput data sets. It can be read-out by VME.⇒ The maximum number of output data sets perevent can be programmed by VME.⇒ The input system clock is monitored by a watchdog circuit.5. MESSAGE GENERATORThe Message Generator receives data sets from sev-eral Pretrigger Boards and transforms them to mes-sages, which contain all necessary  information ac-cording to a standard, which is accepted by the TrackFinding Unit TFU of the HERA-B Level-1 Trigger.Fig.4 shows a block diagram of the main components.5.1 Handshake LogicThe Handshake Logic is responsible for the datatransfer protocol between connected Pretrigger Boardsand Message Generator. The eight DAV flags indicat-ing on which PTB a data set is available are storedperiodically into the input register of an 8-bit Encoder.If there is at least one flag set, the Encoder starts toselect the PTB with the highest number by issuing thecorresponding DAC signal, which open the connectedPTB data port and enables the 27-bit data set to arriveat the Data Input Register, where it is stored togetherwith the 3-bit code of data source (PTB Code). Thenthe next DAV flags are selected one after another, untilVMEM. Msg.VMEHandshakeLogicEncoderVMEDataInput Reg.Test Reg.88327 RoadEncoder   Data  Buffer1119   Look-upTable.  256K*64MessageFIFO256*80585715Const11MUX4:180Test FIFO512*20TTLtoPECLConvert.202202Fig.4: Block Diagram of Message GeneratorDAVDACthe Encoder Input Register is empty and the next DAVpattern is stored. That method ensures, that all PTB’sare selected with equal probability.The data transfer rate between Pretrigger Board andMessage Generator is 25 MHz.5.2 Data Input RegisterThe Data Input Register is the first stage of a 3-stagepipeline. It has a width of 30 bits and distributes 19 bits(RSF Code, PTB Code, Bunch Number, Cycle Bit) tothe Data Buffer and 11 bits (pad bits of the second andthird detector layer) to the Road Encoder.5.3 Road EncoderTogether with the Data Buffer the Road Encoderbuilds the second stage of the process pipeline. It se-quentially encodes up to 18 possible combinationsbetween the 11 input pads, Every 40 nsec a new 5-bitcode is provided. Together with 11 bits of the DataBuffer (RSF Code, PTB Code, Cycle Bit) and twoadditional bits, which have been introduced for multi-ple message generation, it forms the 18-bit address of aLook-up Table, which contains all information neces-sary to compose the message.5.4 Look-up TableThe Look-up Table is a 256K*64 bit static RAMwith an access time of 15 nsec (IDT7MP4045). Foreach possible road 57 out of 64 available bits are usedto provide all relevant parameters. The table can bewritten and read-out by VME.5.5 Message FIFOThe Message FIFO (IDT72205) receives besides thedata bits of the Look-up Table the Bunch Number andsome 15 constant bits reserved for each subdetector. Itis the last stage of the pipeline, which is clocked with25 MHz frequency. It also acts as message buffer,because the output data stream may be disabled by theconnected TFU’s for short times.5.6 Data Transfer to TFUThe Message Generator is connected to severalTFU’s by a 20-bit bus. Therefore the messages have tobe split into four parts by a multiplexer. The resultingpackages are converted to PECL level and transmittedwith a frequency of 100 MHz.5.7 Test FacilitiesAgain the complete Logic of the board can be testedin real time by writing data pattern to the Test Register,starting the evaluation process and reading the result-ing message packages from the Test FIFO, whichmonitors the output data stream.6. SYSTEM LAYOUTPretrigger Board and Message Generator are VMEboards of 9 height units and 340 mm depth. Two clus-ters each consisting of one Message Generator and upto eight Pretrigger Boards are located in one VMEcrate. Four such crates are sufficient for the completeHigh- Pt Level-0 Trigger.In order to reduce the power consumption 3.3Vtechnology has been used as far as it was available.Nevertheless the power consumption  adds up to about1 KW per crate mainly because of the large number ofAutobahn chips used..7. STATUSPrototypes of all three boards have been built andtested successfully. Series production has been startedand the complete system will be available at the end of1999.8. REFERENCES[1] E. Hartouni et al., HERA-B Design Report, DESY-PRC 95/01 (January 1995)[2] V. Balagura et al., NIM A379 (1996) 404A. Schwartz, HERA-B note 97-231V. Popov, HERA-B note 97-252[3] J. Gläß, A. Wurz, HERA-B note 97-011

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