Quantum computers promise to solve computing problems that are currently
intractable using traditional approaches. This can only be achieved if the
noise inevitably present in quantum computers can be efficiently managed at
scale. A key component in this process is a classical decoder, which diagnoses
the errors occurring in the system. If the decoder does not operate fast
enough, an exponential slowdown in the logical clock rate of the quantum
computer occurs. Additionally, the decoder must be resource efficient to enable
scaling to larger systems and potentially operate in cryogenic environments.
Here we introduce the Collision Clustering decoder, which overcomes both
challenges. We implement our decoder on both an FPGA and ASIC, the latter
ultimately being necessary for any cost-effective scalable solution. We
simulate a logical memory experiment on large instances of the leading quantum
error correction scheme, the surface code, assuming a circuit-level noise
model. The FPGA decoding frequency is above a megahertz, a stringent
requirement on decoders needed for e.g. superconducting quantum computers. To
decode an 881 qubit surface code it uses only 4.5% of the available logical
computation elements. The ASIC decoding frequency is also above a megahertz on
a 1057 qubit surface code, and occupies 0.06 mm2 area and consumes 8 mW of
power. Our decoder is optimised to be both highly performant and resource
efficient, while its implementation on hardware constitutes a viable path to
practically realising fault-tolerant quantum computers.Comment: 11 pages, 4 figure