3 research outputs found

    Emerging Run-Time Reconfigurable FPGA and CAD Tools

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    Field-programmable gate array (FPGA) is a post fabrication reconfigurable device to accelerate domain specific computing systems. It offers offer high operation speed and low power consumption. However, the design flexibility and performance of FPGAs are severely constrained by the costly on-chip memories, e.g. static random access memory (SRAM) and FLASH memory. The objective of my dissertation is to explore the opportunity and enable the use of the emerging resistance random access memory (ReRAM) in FPGA design. The emerging ReRAM technology features high storage density, low access power consumption, and CMOS compatibility, making it a promising candidate for FPGA implementation. In particular, ReRAM has advantages of the fast access and nonvolatility, enabling the on-chip storage and access of configuration data. In this dissertation, I first propose a novel three-dimensional stacking scheme, namely, high-density interleaved memory (HIM). The structure improves the density of ReRAM meanwhile effectively reducing the signal interference induced by sneak paths in crossbar arrays. To further enhance the access speed and design reliability, a fast sensing circuit is also presented which includes a new sense amplifier scheme and reference cell configuration. The proposed ReRAM FPGA leverages a similar architecture as conventional SRAM based FPGAs but utilizes ReRAM technology in all component designs. First, HIM is used to implement look-up table (LUT) and block random access memories (BRAMs) for func- tionality process. Second, a 2R1T, two ReRAM cells and one transistor, nonvolatile switch design is applied to construct connection blocks (CBs) and switch blocks (SBs) for signal transition. Furthermore, unified BRAM (uBRAM) based on the current BRAM architecture iv is introduced, offering both configuration and temporary data storage. The uBRAMs provides extremely high density effectively and enlarges the FPGA capacity, potentially saving multiple contexts of configuration. The fast configuration scheme from uBRAM to logic and routing components also makes fast run-time partial reconfiguration (PR) much easier, improving the flexibility and performance of the entire FPGA system. Finally, modern place and route tools are designed for homogeneous fabric of FPGA. The PR feature, however, requires the support of heterogeneous logic modules in order to differentiate PR modules from static ones and therefore maintain the signal integration. The existing approaches still reply on designers’ manual effort, which significantly prolongs design time and lowers design efficiency. In this dissertation, I integrate PR support into VPR – an academic place and route tool by introducing a B*-tree modular placer (BMP) and PR-aware router. As such, users are able to explore new architectures or map PR applications to a variety of FPGAs. More importantly, this enhanced feature can also support fast design automation, e.g. mapping IP core, loading pre-synthesizing logic modules, etc

    uBRAM-based Run-time Reconfigurable FPGA and Corresponding Reconfiguration Methodology

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    With rising demands for high-performance computing and design flexibility of post-fabrication system, reconfigurable architecture has been drawing increasing attentions. However, reconfigurability, advantage of current Field-Programmable Gate Array (FPGA), is severely limited by small capacity of on-chip Static Random Access Memory (SRAM) for storing configuration bits. With emerging high-density and high-performance nano memory devices, opportunities are provided to improve the reconfigurability of the current FPGA's design

    uBRAM-based run-time reconfigurable FPGA and corresponding reconfiguration methodology

    No full text
    With rising demands for high-performance computing and design flexibility of post-fabrication system, reconfigurable architecture has been drawing increasing attentions. However, reconfigurability, advantage of current Field-Programmable Gate Array (FPGA), is severely limited by small capacity of on-chip Static Random Access Memory (SRAM) for storing configuration bits. With emerging high-density and high-performance nano memory devices, opportunities are provided to improve the reconfigurability of the current FPGA's design. In this paper, we demonstrate a novel design of run-time reconfigurable FPGA architecture with distributed unified Block Random Access Memory (uBRAM) based on dense and fastaccess non-volatile memory. The uBRAMs are distributed into the architecture and functioned as unified memory blocks. It can be freely switched between data memory for temporary data storage or configuration memory for configuration bits storage. Such a design supports run-time reconfiguration; meanwhile, it avoids the dedicated area overhead of configuration memory suffered in previous designs. As a consequence, significant area saving and superior design flexibility can be achieved. To fully explore the potential of the proposed architecture, corresponding methods of run-time reconfiguration with uBRAM are introduced, including external/internal run-time reconfiguration, and self-adapting reconfiguration. We take Resistive Random Access Memory (RRAM) as an example of qualified nano memory for case study. The RRAM cells in the uBRAM are aggregated in a 3D High-density Interleaved Memory (3D-HIM) structure to further save area cost. Compared to the conventional FPGA which supports only partial runtime reconfiguration with specific design, experimental results demonstrate the judicious benefits of the proposed architecture on the area saving and the superior design flexibility without scarifying performance requirements and power consumption
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