2 research outputs found
Improving speed of tunnel FETs logic circuits
Tunnel transistors are one of the most attractive steep subthreshold
slope devices which are being investigating to overcome power density
and energy inefficiency exhibited by CMOS technology. These
transistors exhibit asymmetric conduction which can cause sustained
noise voltage pulses (bootstrapping) within digital TFETs circuits
leading to delay degradation. In this paper, we propose a minor
modification of the complementary gate topology to avoid the
bootstrapping problem and show its impact on speed at the circuit level.
Speed improvements up to 33% have been obtained for 8-bit Ripple
Carry Adders when implemented with our solution.Peer reviewe