133 research outputs found

    Long-term survival in patients undergoing cardiac resynchronization therapy: the importance of performing atrio-ventricular junction ablation in patients with permanent atrial fibrillation

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    Aims To investigate the effects of cardiac resynchronization therapy (CRT) on survival in heart failure (HF) patients with permanent atrial fibrillation (AF) and the role of atrio-ventricular junction (AVJ) ablation in these patients. Methods and results Data from 1285 consecutive patients implanted with CRT devices are presented: 1042 patients were in sinus rhythm (SR) and 243 (19%) in AF. Rate control in AF was achieved by either ablating the AVJ in 118 patients (AVJ-abl) or prescribing negative chronotropic drugs (AF-Drugs). Compared with SR, patients with AF were significantly older, more likely to be non-ischaemic, with higher ejection fraction, shorter QRS duration, and less often received ICD back-up. During a median follow-up of 34 months, 170/1042 patients in SR and 39/243 in AF died (mortality: 8.4 and 8.9 per 100 person-year, respectively). Adjusted hazard ratios were similar for all-cause and cardiac mortality [0.9 (0.57-1.42), P = 0.64 and 1.00 (0.60-1.66) P = 0.99, respectively]. Among AF patients, only 11/118 AVJ-abl patients died vs. 28/125 AF-Drugs patients (mortality: 4.3 and 15.2 per 100 person-year, respectively, P < 0.001). Adjusted hazard ratios of AVJ-abl vs. AF-Drugs was 0.26 [95% confidence interval (CI) 0.09-0.73, P = 0.010] for all-cause mortality, 0.31 (95% CI 0.10-0.99, P = 0.048) for cardiac mortality, and 0.15 (95% CI 0.03-0.70, P = 0.016) for HF mortality. Conclusion Patients with HF and AF treated with CRT have similar mortality compared with patients in SR. In AF, AVJ ablation in addition to CRT significantly improves overall survival compared with CRT alone, primarily by reducing HF deat

    RISC-V-Based Platforms for HPC: Analyzing Non-functional Properties for Future HPC and Big-Data Clusters

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    High-Performance Computing (HPC) have evolved to be used to perform simulations of systems where physical experimentation is prohibitively impractical, expensive, or dangerous. This paper provides a general overview and showcases the analysis of non-functional properties in RISC-V-based platforms for HPCs. In particular, our analyses target the evaluation of power and energy control, thermal management, and reliability assessment of promising systems, structures, and technologies devised for current and future generation of HPC machines. The main set of design methodologies and technologies developed within the activities of the Future and HPC &amp; Big Data spoke of the National Centre of HPC, Big Data and Quantum Computing project are described along with the description of the testbed for experimenting two-phase cooling approaches

    A novel dual-walled CNT bus architecture with reduced cross-coupling features

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    Carbon Nano Tubes (CNTs) have been widely proposed as interconnect fabric for nano and very deep sub-micron (silicon-based) technologies due to their robustness to electromigration. In this paper, a novel bus architecture with low crosstalk features is proposed. It is made of dual-walled nanotubes (DWNTs) arranged in parallel. It achieves reductions up to 72% of the crosstalk-induced delay, and up to 76% for the crosstalk-induced peak voltage, at a modest area increase. Therefore, the proposed bus arrangement significantly improves performance and provides reliable operation in an interconnect

    Error correcting code analysis for cache memory high reliability and performance

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    In this paper we address the issue of improving ECC correction ability beyond that provided by the standard SEC/DED Hsiao code. We analyze the impact of the standard SEC/DED Hsiao ECC and for several double error correcting (DEC) codes on area overhead and cache memory access time for different codeword sizes and code-segment sizes, as well as their correction ability as a function of codeword/code-segment sizes. We show the different trade-offs that can be achieved in terms of impact on area overhead, performance and correction ability, thus giving insight to designers for the selection of the optimal ECC and codeword organization/code-segment size for a given application

    Secure communication protocol for wireless sensor networks

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    We propose a new communication protocol for wireless sensor networks, allowing to make them secure with respect to malicious attacks. Compared to standard secure protocols (e.g., the IEEE 802.15.4 and the ZigBee), the one we propose allows to increase security significantly, at negligible impact on node complexity. A possible hardware scheme to implement our protocol is also proposed

    Message from the Editor-in-Chief

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    Presents the introductory editorial for this issue of the publication

    2. ATPG

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    8. Fault Tolerance_1

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