A genetic based neuro-fuzzy controller for thermal processes

This paper presents a neuro-fuzzy network where all its parameters can be tuned simultaneously using Genetic Algorithms. The approach combines the merits of fuzzy logic theory, neural networks and genetic algorithms. The proposed neuro-fuzzy network does not require a priori knowledge about the system and eliminates the need for complicated design steps like manual tuning of input-output membership functions, and selection of fuzzy rule base. Although, only conventional genetic algorithms have been used, convergence results are very encouraging. A well known numerical example derived from literature is used to evaluate and compare the performance of the network with other modelling approaches. The network is further implemented as controller for two simulated thermal processes and their performances are compared with other existing controllers. Simulation results show that the proposed neuro-fuzzy controller whose all parameters have been tuned simultaneously using GAs, offers advantages over existing controllers and has improved performance.Facultad de Informátic

A genetic based neuro-fuzzy controller for thermal processes

This paper presents a neuro-fuzzy network where all its parameters can be tuned simultaneously using Genetic Algorithms. The approach combines the merits of fuzzy logic theory, neural networks and genetic algorithms. The proposed neuro-fuzzy network does not require a priori knowledge about the system and eliminates the need for complicated design steps like manual tuning of input-output membership functions, and selection of fuzzy rule base. Although, only conventional genetic algorithms have been used, convergence results are very encouraging. A well known numerical example derived from literature is used to evaluate and compare the performance of the network with other modelling approaches. The network is further implemented as controller for two simulated thermal processes and their performances are compared with other existing controllers. Simulation results show that the proposed neuro-fuzzy controller whose all parameters have been tuned simultaneously using GAs, offers advantages over existing controllers and has improved performance.Facultad de Informátic

Japanese Encephalitis Outbreak, India, 2005

An outbreak of viral encephalitis occurred in Gorakhpur, India, from July through November 2005. The etiologic agent was confirmed to be Japanese encephalitis virus by analyzing 326 acute-phase clinical specimens for virus-specific antibodies and viral RNA and by virus isolation. Phylogenetic analysis showed that these isolates belonged to genogroup 3

Pigeonpea

Pigeonpea is one of the major grain legumes grown in the tropics and subtropics of the world that forms a significant component of the diet due to its high protein content. Most of the differences in potential and realized yields in pigeonpea have been attributed to several biotic and abiotic constraints; besides the low productivity potential of marginal lands, where this crop is commonly grown. Of the various constraints limiting pigeonpea production, insect pests cause substantial damages. Conventional breeding efforts in pigeonpea crop improvement have been successful in producing improved seed quality and reduction of crop maturity duration. Nevertheless, genetic improvement of pigeonpea has been restricted due to the nonavailability of better genetic resources and strong sexual barriers between the cultivated and wild species. The recent developments in plant genetic engineering have provided immense potential in overcoming some of these constraints, thereby, offering opportunities for its successful integration with conventional crop improvement strategies. This chapter describes the pigeonpea crop, various constraints to its productivity, recent developments in its breeding, and emerging transgenic innovations that could play a significant role in the improvement of pigeonpea crop. We also highlight the current status of pigeonpea transgenics and related biosafety and IPR issues for the successful application of this technology in the near future

Prophylactic use of Midazolam, Ketamine, and Ketamine plus Midazolam for prevention of perioperative shivering during spinal anaesthesia in patients undergoing infraumbilical surgeries: a comparative study

Background: Shivering is a common problem faced by an anaesthesiologist during perioperative period. Shivering occurs during both general anaesthesia and regional anaesthesia but it is more troublesome during neuraxial anaesthesia. To evaluate the effectiveness of intravenous Midazolam, Ketamine and combination of Midazolam with Ketamine in control of shivering.Methods: The study was conducted in 90 ASA I and II patients receiving neuraxial anaesthesia with comparable dose of hyperbaric bupivacaine. The patients were allocated in three groups of 30 each to receive Midazolam 75 mcg/kg, ketamine 0.5 mg/kg and Midazolam 37.5 mcg/kg plus Ketamine 0.25 mg/kg IV after the appearance of shivering. Disappearance and recurrence of shivering as well as temperature and haemodynamics were recorded with scheduled intervals.Results: IV Midazolam plus Ketamine at the dose of 37.5 mcg/kg and 0.25 mg/kg is more effective in prophylaxis of shivering than IV Midazolam 75 mcg/kg or IV Ketamine 0.5 mg/kg. Small number of patients showed, clinically as well as statistically insignificant, incidence of hypotension, bradycardia and respiratory depression of various degrees at various time intervals.Conclusions: Thus, IV Midazolam plus Ketamine at the dose of 37.5 mcg/kg and 0.25 mg/kg IV is more effective in prophylaxis of shivering than IV Midazolam 75 mcg/kg or IV Ketamine 0.5 mg/kg following subarachnoid blockade for infra umbilical surgery. The side effects like Hypotension, nausea, vomiting and pruritus are also very less with combination and prove that it is a better agent for prophylaxis of shivering following regional anesthesia

Prevalence of rtt among ever married women (15-49 years age group) in rajeev nagar (urban slum) Of dehra dun

<p class="Bodytext201">Objective To assess the prevalence of RTI among ever married women by using Syndromic approach.</p><p class="Bodytext201">Study design Cross- Sectional study.</p><p class="Bodytext201">SettingCross- Sectional study.</p><p class="Bodytext201">Setting urban slum, Rajeev Nagar, Dehra Dun.</p><p class="Bodytext201">Participants Ever married women in 15 - 49 years age group.</p><p class="Bodytext201">Study periodJanuary- April 2003.</p><p class="Bodytext201">Study variablesRTI, Occupation, S.E.S.</p><p class="Bodytext251">Statistical analysis Percentage.</p><p class="Bodytext201">ResultPrevalence of RTIs was found to be 7%. It was found to be maximum (57.14%) in laborer's and in women belonging to the lower middle class (65.7%). Commonest symptoms of RTIs were pain lower abdomen (74.2%), burning</p><p class="Bodytext201">micturition (17.14%) and vulval itching (17.14%).</p

DESIGN AND IMPLEMENTATION OF PARTIALLY RECONFIGURABLE FP-AU 1 2 3

Abstract In this paper we present the partial reconfiguration of floating point arithmetic unit that improves the area occupied by floating point arithmetic unit and also makes this unit flexible to operate in a rapidly changing environment. The hardware resources occupied by this unit have been reduced through time-sharing them between modules. Since the FP-AU occupies a significant amount of silicon area in any application due to wide dynamic range, our proposed design shows a very efficient area reduction technique for FP-AU. Partial reconfiguration is the ability of certain Field Programmable Gate Arrays (FPGAs) to reconfigure only selected portions of their programmable hardware while other portions continue to operate undisturbed. A FPGA can be partially reconfigured using a partial bitstream. We can use such a partial bitstream to change the structure of one part of an FPGA design as the rest of the device continues to operate and this reduces the reconfiguration time. The floating point arithmetic unit is modeled in VHDL and synthesized with Xilinx ISE tools. The floating point arithmetic modules are designed for Virtex-2 Pro XC2VP50 FPGA