A Fast Sequential Learning Technique for Real Circuits with Application to Enhancing ATPG Performance

This paper presents an efficient and novel method for sequential learning of implications, invalid states, and tied gates. It can handle real industrial circuits, with multiple clock domains and partial set/reset. The application of this method to improve the efficiency of sequential ATPG is also demonstrated by achieving higher fault coverages and lower test generation times

The Pitfalls of Necessary Assignments

It has been shown that, finding necessary assignments during a search process, such as Automatic Test Pattern Generation (ATPG) process, can significantly improve its search performance. The techniques to find necessary assignments include static learning, dynamic learning, and recursive learning. All these techniques did improve ATPG performance. However, in our experience with real circuits, we found that necessary assignments can create unnecessary requirements in an ATPG process. Sometimes, these unnecessary requirements are not justifiable such that a testable fault may be mistaken as untestable

The Pitfalls of Necessary Assignments

It has been shown that, finding necessary assignments during a search process, such as Automatic Test Pattern Generation (ATPG) process, can significantly improve its search performance. The techniques to find necessary assignments include static learning, dynamic learning, and recursive learning. All these techniques did improve ATPG performance. However, in our experience with real circuits, we found that necessary assignments can create unnecessary requirements in an ATPG process. Sometimes, these unnecessary requirements are not justifiable such that a testable fault may be mistaken as untestable

Enhancing delay fault coverage through low power segmented scan

Abstract- Reducing power dissipation during test has been an active area of academic and industrial research for the last few years and numerous low power DFT techniques and test generation procedures have been proposed. Segmented scan [17-20] has been shown to be an effective technique in addressing test power issues in industrial designs [18]. To achieve higher shipped product quality, tests for delay faults are becoming essential components of manufacturing test. This paper demonstrates, for the first time, that segmented scan facilitates increased delay fault without degrading the reduction of the switching activity obtained by segmented scan. The increased transition delay fault coverage is achieved through careful selection of the capture cycle application. Experimental results on larger ISCAS-89 benchmarks show that using three segments, on average, fault coverage using launch off capture can be increased by about 5.8 % while simultaneously reducing the peak switching activity caused by capture cycles by over 24.8%

A fast sequential learning technique for real circuits with application to enhancing ATPG performance

This paper presents an efficient and novel method for sequential learning of implications, invalid states, and tied gates. It can handle real industrial circuits, with multiple clock domains and partial set/reset. The application of this method to improve the efficiency of sequential ATPG is also demonstrated by achieving higher fault coverages and lower test generation times. 2

Test Generation for Timing-Critical Transition Faults

Timing-aware ATPG [1] has been shown to be an effective method for generating high-quality test sets that detect small delay defects through the longest paths. However, this method usually results in a much higher test pattern count than the traditional transition fault test generation. In this paper, we propose a new criterion that identifies a subset of transition faults to be targeted by the timing-aware ATPG in order to reduce test pattern count while minimizing the impact on the overall delay test quality. The new criterion utilizes the minimal static slack to classify certain transition faults as timing-critical. The test pattern count reduction is achieved by restricting the timing-aware ATPG to targeting the timing-critical transition faults while using traditional transition fault test generation for the remaining transition faults. The experimental results for the industrial circuits show the effectiveness of the proposed method. 1