Modification of HF-treated silicon (100) surfaces by scanning tunneling microscopy in air under imaging conditions

The modification of HF-etched silicon (100) surface with a scanning tunneling microscope(STM) operated in air is studied for the first time in samples subjected to the standard HF etching without the follow-up rinsing in H2O. The modifications are produced in air under normal STM imaging conditions (V t =−1.4 V and I t =2 nA). The simultaneous acquisition of topographical, current image tunneling spectroscopy and local barrier-height images clearly shows that the nature of the modification is not only topographical but also chemical. The features produced with a resolution better than 25 nm are attributed to a tip-induced oxidation enhanced by the presence of fluorine on the surface

Monolithic mass sensor fabricated using a conventional technology with attogram resolution in air conditions

Premi a l'excel·lència investigadora. Àmbit de les Ciències Tecnològiques. 2008Monolithic mass sensors for ultrasensitive mass detection in air conditions have been fabricated using a conventional 0.35 μm complementary metal-oxide-semiconductor (CMOS) process. The mass sensors are based on electrostatically excited submicrometer scale cantilevers integrated with CMOS electronics. The devices have been calibrated obtaining an experimental sensitivity of 6×10−11 g/cm2 Hz equivalent to 0.9 ag/Hz for locally deposited mass. Results from time-resolved mass measurements are also presented. An evaluation of the mass resolution have been performed obtaining a value of 2.4×10−17 g in air conditions, resulting in an improvement of these devices from previous works in terms of sensitivity, resolution, and fabrication process complexity

Stress and aging minimization in photoplastic AFM probes

Photostructurable epoxy based resists, like SU-8, are soft materials with a Young's Modulus around 4 GPa, which makes them particularly suitable as base material to fabricate Atomic Force Microscopy (AFM) probes for non-destructive analysis of fragile samples such as biological materials. In this work, it is shown how by introducing an appropriate processing step consisting of a hard bake, the built-in stress gradient of the final structure was considerably reduced. This improved probes properties such as initial bending and aging and proved the epoxy based resists as good candidates for the low-cost fabrication of micromechanical systems (MEMS) and devices in general. (C) 2008 Elsevier B.V. All rights reserved

Emerging Nanopatterning Methods based on MEMS Technology

The development of nanosystems and nano-devices demands for patterning methods in the nanoscale. To bring them to the market, there is a need for fast, low-cost nanopatterning methods. In addition, an increased flexibility is important for the engineering of multimaterial and multifunctional nano/micro-electro-mechanical systems (NEMS/MEMS), such as polymer-based electronic and sensor devices, 3D microfluidic systems, and bio-analytical systems. A series of alternative surface micro/nanopatterning methods based on MEMS technology are currently being developed, e.g. local fluidic dispensing and shadow-mask deposition (nanostencil lithography). These methods rely on locally adding material onto the substrate without the need for resist layers, exposure and etch steps. MEMS-based nanopatterning can be implemented in various manners: as scanning devices for the flexible, serial, writing of nanopatternings, as replication tools for the copying of an existing pattern, or as parallel scanning MEMS systems combining both, flexibility and increased aerial through-put. Figure 1 summarizes some existing methods that include MEMS tools. Nanostencil lithography is a resistless, single step patterning method based on direct, local deposition of material on an arbitrary surface through a solid-state membrane, e.g. a 200-nm thick silicon nitride (SiN) membrane. Although the method faces several challenges in terms of membrane fabrication at 100-nm scale, gap control, mechanical stability, aperture clogging, alignment for multi-layer patterning, etc. the technique has tremendous advantages for parallel processing. We have studied patterning by stencil lithography on various surfaces including CMOS chips. Figure 2 shows recent results of nanostencil for the patterning of CMOS wafer. Dispensing of liquid at the nanometer scale has high interest for addressing local functionalization of surfaces and development of nanobiosensors and nanobiochips. Atomic force based technology can be used to locally deposit small quantity of liquid. MEMS technology can be used to fabricate arrays of silicon micro-levers with integrated read-out (piezoresistive) and fluidics systems, so that the deposition can be performed in a controllable and precise way. Two approaches are being developed: modfication of conventional AFM cantilevers and development of dedicated devices

Determining radial breathing mode frequencies of single-walled carbon nanotubes with an atomic force microscope

We report on the experimental determination of the radial breathing mode frequency ($\simeq 5$ THz) of individual single-walled carbon nanotubes by nanoindentation measurements performed with an Atomic Force Microscope using commercial microfabricated silicon cantilevers with ultrasharp tips, evidencing the sensitivity of such instruments to frequencies in the THz range, well above the resonance frequencies of the cantilevers ($\sim 130$ kHz)

MONOLITHIC INTEGRATION OF NANOMECHANICAL RESONATORS WITH CMOS CIRCUITRY: FULL-WAFER NANOPATTERNING BY NANOSTENCIL LITHOGRAPHY

For the purpose of integrating nanomechanical structures with CMOS circuitry, nanostencil lithography ensures parallel patterning for rapid processing at wafer scale and nanometer-sized features definition. Moreover, this patterning technique is compatible with CMOS substrates given that it does not alter circuitry performance. However, a major limitation in nanostencil lithography is gap-induced pattern blurring naturally occurring if a planar stencil is used in combination with a substrate containing topography (e.g. CMOS). This phenomenon has been characterized and a corrective technique is implemented in order to eliminate the blurring