A novel topology for a HEMT negative current mirror

A new solution for the implementation of a HEMT negative current source is presented. The topology can be also profitably employed as a current mirror and as an active load in high-gain MMICs voltage amplifiers. A small-signal model of the proposed circuit is developed which allows to find accurate expressions for the required transfer functions (i.e., the output impedance of the current source, and the current gain of the circuit when operated as a current mirror). Design examples using Philips PML ED02AH GaAs PHEMT process are provided. Spice simulations show that a 10- kW output impedance for the current source and a 35dB voltage gain for a differential pair loaded with the proposed current mirror are easily achieved

Calibration of pipeline ADC with pruned Volterra kernels

A Volterra model is used to calibrate a pipeline ADC simulated in Cadence Virtuoso using the STMicroelectronics CMOS 45 nm process. The ADC was designed to work at 50 MSps, but it is simulated at up to 125 MSps, proving that calibration using a Volterra model can significantly increase sampling frequency. Equivalent number of bits (ENOB) improves by 1-2.5 bits (6-15 dB) with 37101 model parameters. The complexity of the calibration algorithm is reduced using different lengths for each Volterra kernels and performing iterative pruning. System identification is performed by least squares techniques with a set of sinusoids at different frequencies spanning the whole Nyquist band. A comparison with simplified Volterra models proposed in the literature shows better performance for the pruned Volterra model with comparable complexity, improving linearity by as much as 1.5 bits more than the other techniques

Housing market trend and rail transport investments in the city of Naples

Rail transport investments can influence housing market trends, as demonstrated in the literature. However many empirical researches highlight that different results can derive from different urban context applications and that each case should be threaten separately. It is for this reason that this paper is focused on the single case of the city of Naples, where many rail transport investments have been carried out in the last decades. The aim of this study is to give an interpretation of the housing values changes due to the opening of new metro stations. This study applies GIS tools in order to show the spatial distribution and the intensity of rail impacts in different areas of the urban system from 1994 to 2004. This study shows that the extent of the impacts varies from place to place and the effects intensity requires the presence of several complementary factors such as central location of the new stations and the presence of urban planning policies in the transit corridors. This again testifies how housing market is strictly related to the infrastructures investments planning and urban design

An all-digital clock generator firm-core based on differential fine-tuned delay for reusable microprocessor cores

Clock generator cores play an increasingly important role in the VU1 design of embedded microprocessors supporting specialized power management modes. We present a fully digital. standardcell-based design of a specialized PLL architecture that can be recompiled on different cell libraries. On a 0.45 μm CMOS implementation. the circuit features a 16 ps jitter, 19.5-to-79 MHz frequency range with a39KHz input. and less than 50 clock cycles wakeup time. © 2001 IEEE

A Simple Technique for Fast Digital Background Calibration of A/D Converters

A modification of the background digital calibration procedure for A/D converters by Li and Moon is proposed, based on a method to improve the speed of convergence and the accuracy of the calibration. The procedure exploits a colored random sequence in the calibration algorithm, and can be applied both for narrowband input signals and for baseband signals, with a slight penalty on the analog bandwidth of the converter. By improving the signal-to-calibration-noise ratio of the statistical estimation of the error parameters, our proposed technique can be employed either to improve linearity or to make the calibration procedure faster. A practical method to generate the random sequence with minimum overhead with respect to a simple PRBS is also presented. Simulations have been performed on a 14-bit pipeline A/D converter in which the first 4 stages have been calibrated, showing a 15 dB improvement in THD and SFDR for the same calibration time with respect to the original technique