118 research outputs found

    Maternal mortality in a tertiary care centre in North India: a retrospective study

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    Background: The World Health Organization (WHO) estimates that, of 536,000 maternal deaths occurring globally each year, 136,000 take places in India. Maternal death has serious implications to the family, the society and the nation. It deprives the surviving infant of mother's care. This study was done to assess maternal mortality in a tertiary care centre in north India where large numbers of patients are referred from the peripheral centers and the rural parts. This study was done to assess the causes of maternal mortality and suggest remedial measures to reduce the same. Objective of present study was to assess the causes of maternal death over a period of one year at G.M.C Amritsar, India.Methods: A retrospective hospital based study of 22 maternal deaths over a period of 1 year from June 2012 to June 2013. The information regarding demographic profile and reproductive parameters were collected and results were analyzed.Results: Over the study period, there were 22 deaths and 7272 live births (Majority were referral from other districts all over Punjab). Most common direct cause of maternal mortality was haemorrhage and anemia was the most common indirect cause. Most maternal deaths were seen in patients from rural areas, unbooked, illiterate patients and patients from low socioeconomic status.Conclusions: Proper health education should be given to the women; early registration of antenatal cases should be done which allows for rapid diagnosis and treatment of high risk cases. Also constructing a well equipped health care facility with trained staff and prompt transport facilities for early referral can bring down the maternal mortality rate in our country

    Synthesis Approach of 2D Mesh Network Inter Communication (2D-2D) using Network on Chip

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    The solution for the multiprocessor system architecture is Application specific Network on Chip (NOC) architectures which are emerging as a leading technology. Modeling and simulation of multilevel network structure and synthesis for custom NOC can beneficial in addressing several requirements such as bandwidth, inter process communication, multitasking application use, deadlock avoidance, router structures and port bandwidth. The paper emphasizes on the network on chip modeling and synthesis of 2D network and intercommunication among multilevel 2D networks. NOC synthesis environment provides transaction level network modeling and address all the requirements together in an integrated chip. In the paper consideration is done for 2D, 8 x 8 network and similar networks are considered which are identified by their specific network address. NOC chip is developed using VHDL programming language. Design is implemented in Xilinx 14.2 VHDL software, functional simulation is carried out in Modelsim 10.1 b, student edition and synthesis process is carried out on Digilent Sparten -3E FPGA