4 research outputs found

    An efficient unused integrated circuits detection algorithm for parallel scan architecture

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    In recent days, many integrated circuits (ICs) are operated parallelly to increase switching operations in on-chip static random access memory (SRAM) array, due to more complex tasks and parallel operations being executed in many digital systems. Hence, it is important to efficiently identify the long-duration unused ICs in the on-chip SRAM memory array layout and to effectively distribute the task to unused ICs in SRAM memory array. In the present globalization, semiconductor supply chain detection of unused SRAM in large memory arrays is a very difficult task. This also results in reduced lifetime and more power dissipation. To overcome the above-mentioned drawbacks, an efficient unused integrated circuits detection algorithm (ICDA) for parallel scan architecture is proposed to differentiate the ‘0’ and ‘1’ in a larger SRAM memory array. The proposed architecture avoids the unbalancing of ‘0’ and ‘1’ concentrations in the on-chip SRAM memory array and also optimizes the area required for the memory array. As per simulation results, the proposed method is more efficient in terms of reliability, the detection rate in both used and unused ICs and reduction of power dissipation in comparison to conventional methods such as backscattering side-channel analysis (BSCA) and network attached storage (NAS) algorithm

    An efficient reconfigurable peak cancellation model for peak to average power ratio reduction in orthogonal frequency division multiplexing communication system

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    The peak to average power ratio (PAPR) in orthogonal frequency division multiplexing (OFDM) communication system will be reduced using reconfigurable peak cancellation (RPC). RPC will also aid in improves the error vector magnitude (EVM) and reduces adjacent channel leakage ratio (ACLR) in OFDM communication system. The proposed RPC design methodology and practical implementation using field programmable gate array (FPGA) are discussed. The proposed RPC has been demonstrated using VIRTEX-7 XC7Z100 dual-core FPGA device with less hardware difficulty and minimum utilization of FPGA resources. The proposed RPC improves the efficiency of OFDM communication process by reducing complementary cumulative distribution function (CCDF) with respect to instantaneous power in dB. A comparison analysis was done between the existing selective mapping (SLM) method with proposed RPS method with respect FPGA resource utilization. The proposed RPC is implemented using VIRTEX-7 XC7Z100 dual-core FPGA device. Its effectively utilizing sub-carriers, fast Fourier transform (FFT) filter, bandwidth, and sampling frequency. Due to parallel switching operation, it reduces the PAPR, ACLR and improves EVM in OFDM signal with less hardware complexity

    An efficient reconfigurable geographic routing congestion control algorithm for wireless sensor networks

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    In recent times, huge data is transferred from source to destination through multi path in wireless sensor networks (WSNs). Due to this more congestion occurs in the communication path. Hence, original data will be lost and delay problems arise at receiver end. The above-mentioned drawbacks can be overcome by the proposed efficient reconfigurable geographic routing congestion control (RgRCC) algorithm for wireless sensor networks. the proposed algorithm efficiently finds the node’s congestion status with the help queue length’s threshold level along with its change rate. Apart from this, the proposed algorithm re-routes the communication path to avoid congestion and enhances the strength of scalability of data communication in WSNs. The proposed algorithm frequently updates the distance between the nodes and by-pass routing holes, common for geographical routing. when the nodes are at the edge of the hole, it will create congestion between the nodes in WSNs. Apart from this, more nodes sink due to congestion. it can be reduced with the help of the proposed RgRCC algorithm. As per the simulation analysis, the proposed work indicates improved performance in comparison to conventional algorithm. By effectively identifying the data congestion in WSNs with high scalability rate as compared to conventional method

    A novel smart contract based blockchain with sidechain for electronic voting

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    Several countries have been researching digital voting methods in order to overcome the challenges of paper balloting and physical voting. The recent coronavirus disease 2019 (COVID-19) epidemic has compelled the remote implementation of existing systems and procedures. Online voting will ultimately become the norm just like unified payments interface (UPI) payments and online banking. With digital voting or electronic voting (e-voting) a small bug can cause massive vote rigging. E-voting must be honest, exact, safe, and simple. E-voting is vulnerable to malware, which can disrupt servers. Blockchain’s end-to-end validation solves these problems. Three smart contracts-voter, candidate, and voting-are employed. The problem of fraudulent actions is addressed using vote coins. Vote coins indicate voter status. Sidechain technology complements blockchain. Sidechains improve blockchain functionality by performing operations outside of blockchains and delivering the results to the mainchain. Thus, storing the encrypted vote on the sidechain and using the decrypted result on the mainchain reduces cost. Building access control policies to grant only authorized users’ access to the votes for counting is made simpler by this authorization paradigm. Results of the approach depict the proposed e-voting system improves system security against replay attacks and reduces the processing cost as well as processing time