40 research outputs found

    Ultra-low power circuits using graphene p-n junctions and adiabatic computing

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    Recent works have proven the functionality of electrostatically controlled graphene p–n junctions that can serve as basic primitive for the implementation of a new class of compact graphene-based reconfigurable multiplexer logic gates. Those gates, referred as RG-MUXes, while having higher expressive power and better performance w.r.t. standard CMOS gates, they also have the drawback of being intrinsically less power/energy efficient. In this work we address this problem from a circuit perspective, namely, we revisit RG-MUXes as devices that can operate adiabatically and hence with ultra-low (ideally, almost zero) power consumption. More specifically, we show how to build basic logic gates and, eventually, more complex logic functions, by appropriately interconnecting graphene-based p–n junctions as to implement the adiabatic charging principle. We provide a comparison in terms of power and performance against both adiabatic CMOS and their non-adiabatic graphene-based counterparts; characterization results collected from SPICE simulations on a set of representative functions show that the proposed ultra-low power graphene circuits can operate with 1.5–4 orders of magnitude less average power w.r.t. adiabatic CMOS and non-adiabatic graphene counterparts respectively. When it comes to performance, adiabatic graphene shows 1.3 (w.r.t. adiabatic CMOS) to 4.5 orders of magnitude (w.r.t. non-adiabatic technologies) better power-delay product

    Schottky‐barrier graphene nanoribbon field‐effect transistors‐based field‐programmable gate array's configurable logic block and routing switch

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    Configurable electronic devices have been developed to provide more flexibility in the advanced digital system design, which needs more device density and there by relies on device scaling. Besides, International Technology Roadmap for Semiconductor (ITRS) has predicted scaling limitation for conventional silicon (Si)‐based devices. Researches on post‐Si materials have proved that carbon could be one of the material which can replaced with Si. Owing to exceptional properties of graphene, designs with graphene‐based devices can replace with Si based ones. This study proposes design and characterisation of graphene‐based simple field‐programmable gate array as a platform of configurable logic structure for future developments. This study focuses on design and characterisation of configurable logic block (CLB), flip‐flop as internal sequential logic devices in CLB, and routing switch, which are designed using graphene nanoribbon field‐effect transistor (GNRFET). The results indicate that proposed CLB is much faster than Si based one and power–delay product of proposed sequential element is much lesser than its counterpart in Si‐based technology. In addition, the proposed GNRFET‐based routing switch requires minimum count of 6 transistors to provide desirable functionality. Foreseeing the feasibility of architecture, this study suggests the possible layout of the proposed logic elements needed for CLB