4 research outputs found

    Low-Power Soft Error Hardened Latch

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    Schottky‐barrier graphene nanoribbon field‐effect transistors‐based field‐programmable gate array's configurable logic block and routing switch

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    Configurable electronic devices have been developed to provide more flexibility in the advanced digital system design, which needs more device density and there by relies on device scaling. Besides, International Technology Roadmap for Semiconductor (ITRS) has predicted scaling limitation for conventional silicon (Si)‐based devices. Researches on post‐Si materials have proved that carbon could be one of the material which can replaced with Si. Owing to exceptional properties of graphene, designs with graphene‐based devices can replace with Si based ones. This study proposes design and characterisation of graphene‐based simple field‐programmable gate array as a platform of configurable logic structure for future developments. This study focuses on design and characterisation of configurable logic block (CLB), flip‐flop as internal sequential logic devices in CLB, and routing switch, which are designed using graphene nanoribbon field‐effect transistor (GNRFET). The results indicate that proposed CLB is much faster than Si based one and power–delay product of proposed sequential element is much lesser than its counterpart in Si‐based technology. In addition, the proposed GNRFET‐based routing switch requires minimum count of 6 transistors to provide desirable functionality. Foreseeing the feasibility of architecture, this study suggests the possible layout of the proposed logic elements needed for CLB
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