35 research outputs found

    Cryogenic Characterization of 180 nm CMOS Technology at 100 mK

    Full text link
    Conventional CMOS technology operated at cryogenic conditions has recently attracted interest for its uses in low-noise electronics. We present one of the first characterizations of 180 nm CMOS technology at a temperature of 100 mK, extracting I/V characteristics, threshold voltages, and transconductance values, as well as observing their temperature dependence. We find that CMOS devices remain fully operational down to these temperatures, although we observe hysteresis effects in some devices. The measurements described in this paper can be used to inform the future design of CMOS devices intended to be operated in this deep cryogenic regime

    A Flexible Front-End Signal Processor for High-Speed Image Sensor Readout

    Get PDF
    AbstractThe High-Speed Image Pre-Processor with Oversampling (HIPPO) is a prototype image sensor readout integrated circuit designed for both high performance and enhanced flexibility. HIPPO's initial target application is the instrumentation of bufferless, column-parallel, soft x-ray Charge-Coupled Device (CCD) image sensors operating at column rates up to 10MHz, enabling 10,000 frames-per-second (fps) video rates. HIPPO's architecture is flexible and allows design tradeoffs between speed, accuracy, and area. This architectural flexibility will enable the fast development of related image sensor and particle detector readout ICs based on HIPPO technology. HIPPO contains 16 channels, each comprising a charge amplifier, a dual-slope correlated double sampler, a sample-and-hold, a multiplexed 12b, 80 MS/s pipelined ADC (one ADC for every 4 channels), and a 480 Mb/s output serializer.HIPPO achieves 35 e-read noise at 10,000 fps for a 1 Mpixel sensor, improving to 24 e-at 5000 fps. HIPPO's charge-domain input obviates the source follower amplifier used in most CCDs and enables the implementation of a fully column-parallel CCD architecture. HIPPO was specifically designed to be flexible in both the sequencing of its operations and in its ability to accommodate input rates potentially varying over an order of magnitude

    Submission of the first fullscale prototype chip for upgraded ATLAS pixel detector at LHC, FE-I4A

    No full text
    A new ATLAS pixel chip FE-I4 is being developed for use in upgraded LHC luminosity environments, including the near-term Insertable B-Layer (IBL) upgrade. FE-I4 is designed in a 130 nm CMOS technology, presenting advantages in terms of radiation tolerance and digital logic density compared to the View the MathML source0.25ÎŒm CMOS technology used for the current ATLAS pixel IC, FE-I3. The FE-I4 architecture is based on an array of 80×336 pixels, each View the MathML source50×250ÎŒm2, consisting of analog and digital sections. In the summer 2010, a first full scale prototype FE-I4A was submitted for an engineering run. This IC features the full scale pixel array as well as the complex periphery of the future full-size FE-I4. The FE-I4A contains also various extra test features which should prove very useful for the chip characterization, but deviate from the needs for standard operation of the final FE-I4 for IBL. In this paper, focus will be brought to the various features implemented in the FE-I4A submission, while also underlining the main differences between the FE-I4A IC and the final FE-I4 as envisioned for IBL

    The FE-I4 Pixel Readout Chip and the IBL Module

    No full text
    FE-I4 is the new ATLAS pixel readout chip for the upgraded ATLAS pixel detector. Designed in a CMOS 130 nm feature size process, the IC is able to withstand higher radiation levels compared to the present generation of ATLAS pixel Front-End FE-I3, and can also cope with higher hit rate. It is thus suitable for intermediate radii pixel detector layers in the High Luminosity LHC environment, but also for the inserted layer at 3.3 cm known as the “Insertable B-Layer” project (IBL), at a shorter timescale. In this paper, an introduction to the FE-I4 will be given, focusing on test results from the first full size FE-I4A prototype which has been available since fall 2010. The IBL project will be introduced, with particular emphasis on the FE-I4-based module concept

    Development of a Large Pixel Chip Demonstrator in RD53 for ATLAS and CMS Upgrades

    No full text
    RD53A is a large scale 65 nm CMOS pixel demonstrator chip that has been developed by the RD53 collaboration for very high rate (3 GHz/cm2) and very high radiation levels (500 Mrad, possibly 1 Grad) for ATLAS and CMS phase 2 upgrades. It features serial powering operation and design variations in the analog and digital pixel matrix for different testing purposes. The design and verification of RD53A are described together with an outline of the plans to develop final pixel chips for the two experiments