38 research outputs found

    ATLAS Pixel Detector and readout upgrades for the improved LHC performance

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    Since the moment it was first started in 2008, the LHC particle accelerator at CERN continued to constantly increase its center-of-mass energy and luminosity. During next years, LHC will undergo two major series of upgrades; after the first one it will reach the design energy of 14 TeV and a luminosity of 2-3·10^34cm-2s-1 (Phase-I ), and in the last phase (Phase-II ) the luminosity will be increased to ~7·10^34cm-2 s-1 . To keep up with the augmented detector performance, the LHC detectors where (and will be) upgraded as well. This work will focus on the ATLAS detector - one of the four main experiments of LHC - and in particular on its Pixel Detector. The ATLAS Pixel Detector was first upgraded in 2015, with the introduction of a new pixel layer - called IBL - to compensate for the B-layer inefficiencies and to increase the tracking performance for Phase-0 and Phase-I. The detector layout, combined with the higher LHC luminosity, led to an increased amount of data to be transmitted and analyzed, constituting a challenge for the read-out system. For this reason the previous readout chain was renovated and two new boards, called IBL-ROD and IBL-BOC, were designed to interface IBL. The second major upgrade involving the ATLAS Pixel Detector will be in 2024-2026, when the Inner Detector will be completely replaced by ITk, entirely made of silicon sensors. To be able to sustain the more difficult conditions, another readout upgrade will be required; the final design has not been decided yet and is still under consideration. This work will give an overview on the ATLAS Pixel Detector and will analyze the motivations that led to its upgrades. The current and future DAQ systems will also be discussed, focusing on the technologies adopted, the detector requirements and the results obtained

    General purpose readout board {\pi} LUP: overview and results

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    This work gives an overview of the PCI-Express board ŌÄ\piLUP, focusing on the motivation that led to its development, the technological choices adopted and its performance. The ŌÄ\piLUP card was designed by INFN and University of Bologna as a readout interface candidate to be used after the Phase-II upgrade of the Pixel Detector of the ATLAS and CMS experiments at LHC. The same team in Bologna is also responsible for the design and commissioning of the ReadOut Driver (ROD) board - currently implemented in all the four layers of the ATLAS Pixel Detector (Insertable B-Layer, B-Layer, Layer-1 and Layer-2) - and acquired in the past years expertise on the ATLAS readout chain and the problematics arising in such experiments. Although the ŌÄ\piLUP was designed to fulfill a specific task, it is highly versatile and might fit a wide variety of applications, some of which will be discussed in this work. Two 7th^{th}-generation Xilinx FPGAs are mounted on the board: a Zynq-7 with an embedded dual core ARM Processor and a Kintex-7. The latter features sixteen 12.5‚ÄČ\,Gbps transceivers, allowing the board to interface easily to any other electronic board, either electrically and/or optically, at the current bandwidth of the experiments for LHC. Many data-transmission protocols have been tested at different speeds, results will be discussed later in this work. Two batches of ŌÄ\piLUP boards have been fabricated and tested, two boards in the first batch (version 1.0) and four boards in the second batch (version 1.1), encapsulating all the patches and improvements required by the first version.Comment: 6 pages, 10 figures, 21th Real Time Conference, winner of "2018 NPSS Student Paper Award Second Prize

    Hog 2023.1: a collaborative management tool to handle Git-based HDL repository

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    Hog (HDL on Git) is an open-source tool designed to manage Git-based HDL repositories. It aims to simplify HDL project development, maintenance, and versioning by using Git to guarantee synthesis and implementation reproducibility and binary file traceability. This is ensured by linking each produced binary file to a specific Git commit, embedding the Git commit hash (SHA) into the binary file via HDL generics stored in firmware registers. Hog is released twice a year, in January and in June. We present here the latest stable version 2023.1, which introduces major novel features, such as the support for Microchip Libero IDE, and the capability to run the Hog Continuous Integration (Hog-CI) workflow with GitHub Actions. A plan to integrate Hog with the OpenCores repository is also described, which is expected to be completed for Hog release 2023.2Comment: Presented at the 3rd Workshop on Open-Source Design Automation (OSDA), 2023 (arXiv:2303.18024

    Search for dark matter produced in association with bottom or top quarks in ‚ąös = 13 TeV pp collisions with the ATLAS detector

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    A search for weakly interacting massive particle dark matter produced in association with bottom or top quarks is presented. Final states containing third-generation quarks and miss- ing transverse momentum are considered. The analysis uses 36.1 fb‚ąí1 of proton‚Äďproton collision data recorded by the ATLAS experiment at ‚ąös = 13 TeV in 2015 and 2016. No significant excess of events above the estimated backgrounds is observed. The results are in- terpreted in the framework of simplified models of spin-0 dark-matter mediators. For colour- neutral spin-0 mediators produced in association with top quarks and decaying into a pair of dark-matter particles, mediator masses below 50 GeV are excluded assuming a dark-matter candidate mass of 1 GeV and unitary couplings. For scalar and pseudoscalar mediators produced in association with bottom quarks, the search sets limits on the production cross- section of 300 times the predicted rate for mediators with masses between 10 and 50 GeV and assuming a dark-matter mass of 1 GeV and unitary coupling. Constraints on colour- charged scalar simplified models are also presented. Assuming a dark-matter particle mass of 35 GeV, mediator particles with mass below 1.1 TeV are excluded for couplings yielding a dark-matter relic density consistent with measurements

    Firmware development and testing for L1/L2 IBL upgrade

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    Il lavoro di questa tesi riguarda principalmente l'upgrade, la simulazione e il test di schede VME chiamate ReadOut Driver (ROD), che sono parte della catena di elaborazione ed acquisizione dati di IBL (Insertable B-Layer). IBL √® il nuovo componente del Pixel Detector dell'esperimento ATLAS al Cern che √® stato inserito nel detector durante lo shut down di LHC; fino al 2012 infatti il Pixel Detector era costituito da tre layer, chiamati (partendo dal pi√Ļ interno): Barrel Layer 0, Layer 1 e Layer 2. Tuttavia, l'aumento di luminosit√† di LHC, l'invecchiamento dei pixel e la richiesta di avere misure sempre pi√Ļ precise, portarono alla necessit√† di migliorare il rivelatore. Cos√¨, a partire dall'inizio del 2013, IBL (che fino a quel momento era stato un progetto sviluppato e finanziato separatamente dal Pixel Detector) √® diventato parte del Pixel Detector di ATLAS ed √® stato installato tra la beam-pipe e il layer B0. Questa tesi fornir√† innanzitutto una panoramica generale dell'esperimento ATLAS al CERN, includendo aspetti sia fisici sia tecnici, poi tratter√† in dettaglio le varie parti del rivelatore, con particolare attenzione su Insertable B-Layer. Su quest'ultimo punto la tesi si focalizzer√† sui motivi che ne hanno portato alla costruzione, sugli aspetti di design, sulle tecnologie utilizzate (volte a rendere nel miglior modo possibile compatibili IBL e il resto del Pixel Detector) e sulle scelte di sviluppo e fabbricazione. La tesi tratter√† poi la catena di read-out dei dati, descrivendo le tecniche di interfacciamento con i chip di front-end, ed in particolare si concentrer√† sul lavoro svolto per l'upgrade e lo sviluppo delle schede ReadOut Drivers (ROD) introducendo le migliorie da me apportate, volte a eliminare eventuali difetti, migliorare le prestazioni ed a predisporre il sistema ad una analisi prestazionale del rivelatore. Allo stato attuale le schede sono state prodotte e montate e sono gi√† parte del sistema di acquisizione dati del Pixel Detector di ATLAS, ma il firmware √® in continuo aggiornamento. Il mio lavoro si √® principalmente focalizzato sul debugging e il miglioramento delle schede ROD; in particolare ho aggiunto due features: - programmazione parallela delle FPGA} delle ROD via VME. IBL richiede l'utilizzo di 15 schede ROD e programmandole tutte insieme (invece che una alla volta) porta ad un sensibile guadagno nei tempi di programmazione. Questo √® utile soprattutto in fase di test; - reset del Phase-Locked Loop (PLL)} tramite VME. Il PLL √® un chip presente nelle ROD che distribuisce il clock a tutte le componenti della scheda. Avere la possibilit√† di resettare questo chip da remoto permette di risolvere problemi di sincronizzazione. Le ReadOut Driver saranno inoltre utilizzate da pi√Ļ layer del Pixel Detector. Infatti oltre ad IBL anche i dati provenienti dai layer 1 e 2 dei sensori a pixel dell‚Äôesperimento ATLAS verranno acquisiti sfruttando la catena hardware progettata, realizzata e testata a Bologna

    ATLAS Pixel Detector and readout upgrades for the improved LHC performance

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    Since the moment it was first started in 2008, the LHC particle accelerator at CERN continued to constantly increase its center-of-mass energy and luminosity. The entire LHC lifetime can be divided into several phases; in the first period the collider was running at an energy of 7-8 TeV and a luminosity of ‚ąľ 10 33 cm ‚ąí2 s ‚ąí1 . After that, the energy was increased to 13 TeV and the luminosity to 1-2¬∑10 34 cm ‚ąí2 s ‚ąí1 (Phase-0 ). During next years, LHC will undergo two more series of upgrades; after the first one it will reach the design energy of 14 TeV and a luminosity of 2-3¬∑10 34 cm ‚ąí2 s ‚ąí1 (Phase-I ), and in the last phase (Phase-II ) the luminosity will be increased to ‚ąľ 7 ¬∑ 10 34 cm ‚ąí2 s ‚ąí1 . To keep up with the augmented detector performance, the LHC detectors where (and will be) upgraded as well. This work will focus on the ATLAS detector - one of the four main experiments of LHC - and in particular on its Pixel Detector. The ATLAS Pixel Detector was first upgraded in 2015, with the introduction of a new pixel layer - called IBL - to compensate for the B-layer inefficiencies and dead pixels and to increase the tracking performance for Phase-0 and Phase-I. IBL features smaller pixel size compared to the other layers, and higher granularity. The detector layout, combined with the higher LHC luminosity, led to an increased amount of data to be transmitted and analyzed, constituting a challenge for the read-out system. For this reason the previous readout chain was completed renovated and two new boards, called IBL-ROD and IBL-BOC, were designed to interface IBL. The two cards provide higher bandwidth and feature more recent technologies and high level control capabilities. Between 2016 and 2018 the collider continued to increase its luminosity, exceed- ing its design value. As a result, the old readout chain still used for the rest of the Pixel Detector was completely saturated, and it was gradually replaced by the new system (IBL-ROD and IBL-BOC). While the hardware is already in place, the firmware and software utilities of the Pixel Detector readout chain are in constant evolution, in order to be able to provide good quality data even at the harsher en- vironmental conditions of Phase-I LHC. The second major upgrade involving the ATLAS Pixel Detector will be in 2024- 2026, when the Inner Detector will be completely replaced by ITk, entirely made of silicon sensors. The new pixel detector will feature even smaller pixels built with 65 nm technology and higher granularity and data rates. To be able to sustain the more difficult conditions, another readout upgrade will be required; the final design has not been decided yet and is still under consideration. Two of the main candidates to implement the final system are the ŌÄLUP project in Bologna - which produced the ŌÄLUP readout board - and the FELIX collaboration - which involves several institutes all over the world and produced the readout card FLX-712, that will be used by some ATLAS sub-detectors during Phase-I upgrade. This work will give an overview on the ATLAS Pixel Detector and will analyze the motivations that led to its upgrades. The current and future DAQ systems will also be discussed, focusing on the technologies adopted, the detector requirements and the results obtained

    Calibrazione di un rilevatore gamma con un flash adc e il software di acquisizione dati dell'esperimento atlas

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    La tesi descrive lo sviluppo di un pezzo di software di acquisizione dati per l'esperimento LUCID di ATLAS al CERN che viene testato nella calibrazione di due rivelatori inorganici cristallini allo ioduro di sodi

    Readout upgrade for the ATLAS Pixel Detector: reasons, status and results

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    This work intends to briefly overview the readout upgrade for the ATLAS Pixel Detector. Two electronic boards compose the readout chain: Back Of Crate and ReadOut Driver. The two boards were designed to interface the chip FEI4, the front-end chip used in Insertable B-Layer, the innermost and most recent layer of the ATLAS Pixel Detector. Due to the characterizing low latency, high bandwidth and system versability, those boards achieved exceptional results and were chosen to replace the readout electronic of Layer 2, Layer 1, the B-Layer and the Disks. In this work the reasons for the ATLAS Pixel Detector readout upgrade will be discussed, as well as the technological solution adopted and the achieved results

    Implementation of a RD53A readout chain using FELIX system and the PiLUP board

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    RD53A is the first prototype of RD53, the pixel detector front-end chip that will be used by the ATLAS and CMS experiments at CERN during HL-LHC, starting operation in 2026. It is implemented using 65 nm technology and it transmits data using up to four lanes running at 1.28 Gbps each. This presentation will describe the implementation of a first readout chain of the RD53A using the ATLAS FELIX card. The readout chain features a third card, called PiLUP, as a protocol converter between RD53A and FELIX, with direct communication planned in future revisions

    Hardware production quality control for the ATLAS Phase-I read-out upgrade

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    The upcoming upgrade of the readout system of the ATLAS experiment at the LHC at CERN is based on the Front-End LInk eXchange (FELIX) system. As part of this upgrade, approximately 120 custom PCIe cards are being produced by an industrial partner, based on a hardware design developed within the collaboration of several institutes and Universities. Such a large production requires detailed Quality Assurance/Quality Control procedures (QA/QC) to ensure the hardware being produced is fully functional and robust
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