78 research outputs found

    Development of a triple well CMOS MAPS device with in-pixel signal processing and sparsified readout capabilities

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    none 39 The SLIM5 collaboration has designed, fabricated and tested several prototypes of CMOS Monolithic Active Pixel Sensors (MAPS). The key feature of these devices, with respect to traditional MAPS is to include, at the pixel level, charge amplification and shaping and a first sparsification structure that interfaces with on-chip digital readout circuits. Via the 3-well option of the applied View the MathML source ST-Microelectronics CMOS technology each pixel includes a charge preamplifier, a shaper, a discriminator, an output latch, while retaining a fill factor of the sensitive area close to 90%. The last device of the family was submitted on Q4 2006 and the tests are ongoing. On this sensor, an on-chip, off-pixel digital readout block (streamout data sparsification) was added to implement, to control and to readout a test matrix built up of 4×4 pixels. It is aimed at proposing solutions that will overcome the readout speed limit of future large-matrix MAPS chips. http://dx.doi.org/10.1016/j.nima.2007.07.135 none G. Batignani; S. Bettarini; F. Bosi; G. Calderini; R. Cenci; M. Dell'Orso; F. Forti P. ; M.A. Giorgi; A. Lusiani; G. Marchiori; F. Morsani; N. Neri; E. Paoloni; G. Rizzo1; J. Walsh; L. Gaioni; M. Manghisoni; V. Re; G. Traversi; M. Bruschi; A. Gabrielli; B. Giacobbe; N. Semprini; R. Spighi; M. Villa; A. Zoccoli; G. Verzellesi; C. Andreoli5; E. Pozzati; L. Ratti; V. Speziali; D. Gamba; G. Giraudo; P. Mereu; L. Bosisio; G. Giacomini; L. Lanceri; I. Rachevskaia; L. Vitale G. Batignani; S. Bettarini; F. Bosi; G. Calderini; R. Cenci; M. Dell'Orso; F. Forti P. ; M.A. Giorgi; A. Lusiani; G. Marchiori; F. Morsani; N. Neri; E. Paoloni; G. Rizzo1; J. Walsh; L. Gaioni; M. Manghisoni; V. Re; G. Traversi; M. Bruschi; A. Gabrielli; B. Giacobbe; N. Semprini; R. Spighi; M. Villa; A. Zoccoli; G. Verzellesi; C. Andreoli5; E. Pozzati; L. Ratti; V. Speziali; D. Gamba; G. Giraudo; P. Mereu; L. Bosisio; G. Giacomini; L. Lanceri; I. Rachevskaia; L. Vital

    Results on Proton-Irradiated 3D Pixel Sensors Interconnected to RD53A Readout ASIC

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    Test beam results obtained with 3D pixel sensors bump-bonded to the RD53A prototype readout ASIC are reported. Sensors from FBK (Italy) and IMB-CNM (Spain) have been tested before and after proton-irradiation to an equivalent fluence of about 11 ×\times 101610^{16} neq\text{n}_{\text{eq}} cm−2^{-2} (1 MeV equivalent neutrons). This is the first time that one single collecting electrode fine pitch 3D sensors are irradiated up to such fluence bump-bonded to a fine pitch ASIC. The preliminary analysis of the collected data shows no degradation on the hit detection efficiencies of the tested sensors after high energy proton irradiation, demonstrating the excellent radiation tolerance of the 3D pixel sensors. Thus, they will be excellent candidates for the extreme radiation environment at the innermost layers of the HL-LHC experiments.Comment: Conference Proceedings of VCI2019, 15th Vienna Conference of Instrumentation, February 18-22, 2019, Vienna, Austria. arXiv admin note: text overlap with arXiv:1903.0196

    CMOS monolithic sensors in a homogeneous 3D process for low energy particle imaging

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    A 3D, through silicon via microelectronic process, capable of face-to-face assembling two 130 nm CMOS tiers in a single bi-layer wafer, has been exploited for the design of monolithic active pixels (MAPS), featuring a deep N-well (DNW) collecting electrode. They are expected to improve on planar CMOS DNW MAPS in terms of charge collection efficiency since most of the PMOS transistors in the front-end electronics, with their N-wells, can be moved to a different layer from that of the DNW sensor. The vertical integration process also requires that one of the two CMOS tiers be thinned down to a mere 6 m to expose the through silicon vias and contact the sandwiched circuits. In this work, results from device simulations of 3D MAPS will be presented. The aim is to evaluate the potential of such a thin sensitive substrate in the detection of low energy particles (in the tens of keV range), in view of possible applications to biomedical imaging

    Results from CHIPIX-FE0, a Small Scale Prototype of a New Generation Pixel Readout ASIC in 65nm CMOS for HL-LHC

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    CHIPIX65-FE0 is a readout ASIC in CMOS 65nm designed by the CHIPIX65 project for a pixel detector at the HL-LHC, consisting of a matrix of 64x64 pixels of dimension 50x50 ÎŒm2. It is fully functional, can work at low thresholds down to 250e− and satisfies all the specifications. Results confirm low-noise, fast performance of both the synchronous and asynchronous front-end in a complex digital chip. CHIPIX65-FE0 has been irradiated up to 600 Mrad and is only marginally affected on analog performance. Further irradiation to 1 Grad will be performed. Bump bonding to silicon sensors is now on going and detailed measurements will be presented. The HL-LHC accelerator will constitute a new frontier for particle physics after year 2024. One major experimental challenge resides in the inner tracking detectors, measuring particle position: here the dimension of the sensitive area (pixel) has to be scaled down with respect to LHC detectors. This paper describes the results obtained by CHIPIX65-FE0, a readout ASIC in CMOS 65nm designed by the CHIPIX65 project as small-scale demonstrator for a pixel detector at the HL-LHC. It consists of a matrix of 64x64 pixels of dimension 50x50 um2 pixels and contains several pieces that are included in RD53A, a large scale ASIC designed by the RD53 Collaboration: two out of three front-ends (a synchronous and an asynchronous architecture); several building blocks; a (4x4) pixel region digital architecture with central local buffer storage, complying with a 3 GHz/cm2 hit rate and a 1 MHz trigger rate maintaining a very high efficiency (above 99%). The chip is 100% functional, either running in triggered or trigger-less mode. All building-blocks (DAC, ADC, Band Gap, SER, sLVS-TX/RX) and very front ends are working as expected. Analog performance shows a remarkably low ENC of 90e-, a fast-rise time below 25ns and low-power consumption (about 4ÎŒA/pixel) in both synchronous and asynchronous front-ends; a very linear behavior of CSA and discriminator. No significant cross talk from digital electronics has been measured, achieving a low threshold of 250e-. Signal digitization is obtained with a 5b-Time over Threshold technique and is shown to be fairly linear, working well either at 80 MHz or with higher frequencies of 300 MHz obtained with a tunable local oscillator. Irradiation results up to 600 Mrad at low temperature (-20°C) show that the chip is still fully functional and analog performance is only marginally degraded. Further irradiation will be performed up to 1 Grad either at low or room temperature, to further understand the level of radiation hardness of CHIPIX65-FE0. We are now in the process of bump bonding CHIPIX65-FE0 to 3D and possibly planar silicon sensors during spring. Detailed results will be presented in the conference paper

    CMS analog front-end: simulations and measurements

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    Simulations and measurements of the Linear analogue front-end used in the RD53B-CMS (CROC) pixel chip. Lots of useful information when having to optimize Analog front-end configuration to specific pixel sensor and specific operation condition

    Test results and prospects for RD53A, a large scale 65 nm CMOS chip for pixel readout at the HL-LHC

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    The CERN RD53 collaboration was founded to tackle the extraordinary challenges associated with the design of pixel readout chips for the innermost layers of particle trackers at future high energy physics experiments. Around 20 institutions are involved in the collaboration, which has the support of both ATLAS and CMS experiments. The goals of the collaboration include the comprehensive understanding of radiation effects in the 65 nm technology, the development of tools and methodology to efficiently design large complex mixed signal chips and, ultimately, the development of a full size readout chip featuring a 400 × 400 pixel array with 50ÎŒm pitch. In August 2017, the collaboration submitted the large scale chip RD53A, integrating a matrix of 400 × 192 pixels and embodying three different analog front-end designs. This work discusses the characteristic of the RD53A chip, with some emphasis on the analog processors, and presents the first test results on the pixel array

    A Charge Sensitive Amplifier in a 28 nm CMOS Technology for Pixel Detectors at Future Particle Colliders

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    This paper is concerned with the design of a Charge Sensitive Amplifier (CSA) in a 28 nm CMOS technology. The CSA discussed in this work is conceived for High Energy Physics (HEP) experiments at next-generation colliders, where pixel detectors will be read out by specific front-end chips, typically including a CSA exploited for charge-to-voltage conversion of the signal delivered by the sensor. The main analog performance parameters of the CSA, also referred to as the pre-amplifier, are assessed here by means of specific Spectre simulations, which are meant to evaluate the behavior of the analog processor in terms of noise, linearity and capability to compensate for very large detector leakage currents. Noise simulations revealed an equivalent noise charge close to 75 electrons rms for typical operating conditions. Up to 50 nA sensor leakage current can be compensated for thanks to the CSA Keummenacher feedback network. The total current consumption of the CSA is close to 2.2 ”A, which, together with a power supply of 0.9 V, translates to a power consumption of 2.0 ”W

    Dynamic Compression of the Signal in a Charge Sensitive Amplifier: Experimental Results

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    This work is concerned with the experimental characterization of a Charge Sensitive Amplifier featuring dynamic signal compression, fast recovery time, low noise and reduced area occupancy. The device takes advantage of the non-linear characteristic of a feedback transistor which behaves like a voltage controlled capacitance. This property has been exploited to fit a wide input dynamic range into the available output swing. The charge amplifier can be operated in synchronous mode at high frame rates, of the order of few MHz, thanks to a wide bandwidth, an improved output stage and a fast reset network. Thanks to the small area occupancy the amplifier is suitable for integration in a 100×100 ÎŒm2 pixel area. All these features make the device a good candidate for applications where a fast frontend with a non-linear response is required, such as in imaging instrumentation for Free Electron Laser experiments. The aim of the paper is to present and discuss the experimental results coming from the characterization of the first prototype of the circuit which has been designed in a 65 nm CMOS technology. The work has been carried out in the frame of the PixFEL Project funded by the INFN, Italy