508 research outputs found

    Design of on-chip data sparsification for a mixed-mode MAPS device

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    The device described in the paper is built up of a bidimensional matrix of Monolithic Active Pixel Sensor (MAPS) and an off-pixel digital readout sparsification circuit. The readout logic is based on std-cells and implements an optimised technique aimed at overcoming the readout speed limit of future large-matrix pixel detectors for particle tracking, by matching the requirements of future HEP experiments. In particular, the readout architecture extends the flexibility of the MAPS devices to be also used in first level triggers in vertex detectors. The work extends a first version of a mixed mode device submitted on Nov. 2006 and implemented with the same technology

    Proposal of a readout technique for low-pitch pixel devices

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    The up-to-date radiation position pixel detectors designed and constructed for high-energy physics, as Large Hadron Collider experiments at CERN, share comparable on-chip readout electronics. They implement full-custom 2D matrixes of sensitive elements, which are basically readout via tokenbased techniques, according to trigger signals. As the readout phase is one of the crucial points of large matrix devices, here it is described a novel readout architecture of pixel devices, which exploits the features of the state-of-the-art deepsubmicron CMOS technologies and could be applied to lowpitch pixel circuits. This allows for future applications not only to general pixel detectors but also to trackers and trigger systems, wherever an on-line data reduction is required

    Hierarchical organization of functional connectivity in the mouse brain: a complex network approach

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    This paper represents a contribution to the study of the brain functional connectivity from the perspective of complex networks theory. More specifically, we apply graph theoretical analyses to provide evidence of the modular structure of the mouse brain and to shed light on its hierarchical organization. We propose a novel percolation analysis and we apply our approach to the analysis of a resting-state functional MRI data set from 41 mice. This approach reveals a robust hierarchical structure of modules persistent across different subjects. Importantly, we test this approach against a statistical benchmark (or null model) which constrains only the distributions of empirical correlations. Our results unambiguously show that the hierarchical character of the mouse brain modular structure is not trivially encoded into this lower-order constraint. Finally, we investigate the modular structure of the mouse brain by computing the Minimal Spanning Forest, a technique that identifies subnetworks characterized by the strongest internal correlations. This approach represents a faster alternative to other community detection methods and provides a means to rank modules on the basis of the strength of their internal edges.Comment: 11 pages, 9 figure

    GPGPU for track finding in High Energy Physics

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    The LHC experiments are designed to detect large amount of physics events produced with a very high rate. Considering the future upgrades, the data acquisition rate will become even higher and new computing paradigms must be adopted for fast data-processing: General Purpose Graphics Processing Units (GPGPU) is a novel approach based on massive parallel computing. The intense computation power provided by Graphics Processing Units (GPU) is expected to reduce the computation time and to speed-up the low-latency applications used for fast decision taking. In particular, this approach could be hence used for high-level triggering in very complex environments, like the typical inner tracking systems of the multi-purpose experiments at LHC, where a large number of charged particle tracks will be produced with the luminosity upgrade. In this article we discuss a track pattern recognition algorithm based on the Hough Transform, where a parallel approach is expected to reduce dramatically the execution time.Comment: 6 pages, 4 figures, proceedings prepared for GPU-HEP 2014 conference, submitted to DESY-PROC-201

    High-Efficiency Digital Readout Systems for Fast Pixel-based Vertex Detectors

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    Particle physics is one of the science branches which heavily relies on most advanced technologies due to the increasing complexity of the problems it has to face. In future colliders, luminosities and beam energies are scaling upwards. These are necessary conditions for the discovery of new physics which both result in a larger amount of data that need to be brought out of the detector. That’s why one of the crucial points for new experiments is the evolution of data acquisition systems. Data acquisition systems employed in particle physics experiments followed the global technology trend and moved towards digital electronics and transmission lines, in this chapter we will describe how the effort of our work has been applied in this direction trying to extend digital processing on the very front-end of the detector. We will show how digital elaboration on the very front-end can help coping with new stringent requirements

    Simulated Hough Transform Model Optimized for Straight-Line Recognition Using Frontier FPGA Devices

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    The use of the Hough transforms to identify shapes or images has been extensively studied in the past using software for artificial intelligence applications. In this article, we present a generalization of the goal of shape recognition using the Hough transform, applied to a broader range of real problems. A software simulator was developed to generate input patterns (straight-lines) and test the ability of a generic low-latency system to identify these lines: first in a clean environment with no other inputs and then looking for the same lines as ambient background noise increases. In particular, the paper presents a study to optimize the implementation of the Hough transform algorithm in programmable digital devices, such as FPGAs. We investigated the ability of the Hough transform to discriminate straight-lines within a vast bundle of random lines, emulating a noisy environment. In more detail, the study follows an extensive investigation we recently conducted to recognize tracks of ionizing particles in high-energy physics. In this field, the lines can represent the trajectories of particles that must be immediately recognized as they are created in a particle detector. The main advantage of using FPGAs over any other component is their speed and low latency to investigate pattern recognition problems in a noisy environment. In fact, FPGAs guarantee a latency that increases linearly with the incoming data, while other solutions increase latency times more quickly. Furthermore, HT inherently adapts to incomplete input data sets, especially if resolutions are limited. Hence, an FPGA system that implements HT is inefficient for small sets of input data but becomes more cost-effective as the size of the input data increases. The document first presents an example that uses a large Accumulator consisting of 1100 x 600 Bins and several sets of input data to validate the Hough transform algorithm as random noise increases to 80% of input data. Then, a more specifically dedicated input set was chosen to emulate a real situation where a Xilinx UltraScale+ was to be used as the final target device. Thus, we have reduced the Accumulator to 280 x  280 Bins using a clock signal at 250 MHz and a few tens input points. Under these conditions, the behavior of the firmware matched the software simulations, confirming the feasibility of the HT implementation on FPGA

    Production and test of a readout chip for the ALICE SDD experiment

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    The paper summarizes the design, the fabrication and test of a chip for the silicon drift detector experiment, part of the A Large Ion Collider Experiment (ALICE) at CERN. The chip performs data reduction via bidimensional compression and packing for the readout chain of the experiment. The chip interfaces with front-end electronics and with the counting room. It is synchronized with a 40 MHz system master clock and configured via a serial signal. The work presents the tests that were performed to characterize the chip and it exploits the final yield of 89% over 700 fabricated chips. The whole tests were performed in laboratory and the chip was also tested in a test beam at CERN in November 2004

    A high throughput Intrusion Detection System (IDS) to enhance the security of data transmission among research centers

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    Data breaches and cyberattacks represent a severe problem in higher education institutions and universities that can result in illegal access to sensitive information and data loss. To enhance the security of data transmission, Intrusion Prevention Systems (IPS, i.e., firewalls) and Intrusion Detection Systems (IDS, i.e., packet sniffers) are used to detect potential threats in the exchanged data. IPSs and IDSs are usually designed as software programs running on a server machine. However, when the speed of exchanged data is too high, this solution can become unreliable. In this case, IPSs and IDSs designed on a real hardware platform, such as ASICs and FPGAs, represent a more reliable solution. This paper presents a packet sniffer that was designed using a commercial FPGA development board. The system can support a data throughput of 10 Gbit/s with preliminary results showing that the speed of data transmission can be reliably extended to 100 Gbit/s. The designed system is highly configurable by the user and can enhance the data protection of information transmitted using the Ethernet protocol. It is particularly suited for the security of universities and research centers, where point-to-point network connections are dominant and large amount of sensitive data are shared among different hosts.Comment: 10 pages, 10 figures, 16th Topical Seminar on Innovative Particle and Radiation Detectors (IPRD23), 25-29 September 2023, Siena, Ital

    A new one-pot synthesis of quinoline-2-carboxylates under heterogeneous conditions

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    Quinoline-2-carboxylates are an important subclass of quinoline derivatives largely present in a variety of biologically active molecules, as well as useful ligands in metal-catalyzed reactions. Herein, we present a new one-pot protocol for synthesizing this class of derivatives starting from beta-nitroacrylates and 2-aminobenzaldehydes. In order to optimize the protocol, we investigated several reaction conditions, obtaining the best results using the 2-tert-butylimino-2-diethylamino- 1,3-dimethylperhydro-1,3,2-diazaphosphorine (BEMP) as solid base, in acetonitrile. Finally, we demonstrated the generality of our approach over several substrates which led to synthesize a plethora of functionalized quinolines-2-carboxylate derivatives in good overall yields
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