40 research outputs found

    Monolithic Active Pixel Matrix with Binary Counters (MAMBO) ASIC

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    Monolithic Active Matrix with Binary Counters (MAMBO) is a counting ASIC designed for detecting and measuring low energy X-rays from 6-12 keV. Each pixel contains analogue functionality implemented with a charge preamplifier, CR-RC{sup 2} shaper and a baseline restorer. It also contains a window comparator which can be trimmed by 4 bit DACs to remove systematic offsets. The hits are registered by a 12 bit ripple counter which is reconfigured as a shift register to serially output the data from the entire ASIC. Each pixel can be tested individually. Two diverse approaches have been used to prevent coupling between the detector and electronics in MAMBO III and MAMBO IV. MAMBO III is a 3D ASIC, the bottom ASIC consists of diodes which are connected to the top ASIC using {mu}-bump bonds. The detector is decoupled from the electronics by physically separating them on two tiers and using several metal layers as a shield. MAMBO IV is a monolithic structure which uses a nested well approach to isolate the detector from the electronics. The ASICs are being fabricated using the SOI 0.2 {micro}m OKI process, MAMBO III is 3D bonded at T-Micro and MAMBO IV nested well structure was developed in collaboration between OKI and Fermilab

    Développement d'un capteur de nouvelle génération et son électronique intégrée pour les collisionneurs futurs

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    Vertex detectors are of great importance in particle physics experiments, as the knowledge of the event flavour is becoming an issue for the physics programme at Future Linear Colliders. Monolithic Active Pixel Sensors (MAPS) based on a novel detector structure have been proposed. Their fabrication is compatible with a standard CMOS process. The sensor is inseparable from thereadout electronics, since both of them are integrated on the same, low-resistivity silicon wafer. The basic pixel configuration comprises only three MOS transistors and a diode collecting the charge through thermal diffusion. The charge is generated inthe thin undepleted epitaxial layer underneath the readout electronics. This approach provides, at low cost, a high resolution and thin device with the whole area sensitive to radiation. Device simulations using the ISE-TCAD package have been carried out to study the charge collection mechanism. In order to demonstrate the viability of the technique, four prototype chips have been fabricated using different submicrometer CMOS processes. The pixel gain has been calibrated using a 55Fe source and thePoisson sequence method. The prototypes have been exposed to high-energy particle beams at CERN. The tests proved excellent detection performances expressed in a single-track spatial resolution of 1.5 μm and detection efficiency close to 100%, resulting from a SNR ratio of more than 30. Irradiation tests showed immunity of MAPS to a level of a few times 1012 n/cm2 and a few hundred kRad of ionising radiation. The ideas for future work, including on-pixel signal amplification, double sampling operation and current mode pixel design are present as well.Les détecteurs de vertex sont importants pour les expériences de la physique des particules, car la connaissance de la saveur présente dans un événement deviendra une question majeure dans le programme de physique auprès du Futur Collisionneur Linéaire. Un capteur monolithique à pixels actifs (MAPS) basé sur une structure originale a été proposé. Le capteur est inséparable de son électronique de lecture, puisque les deux sont intégrés sur la même tranche de silicum basse résistivité qui constitue le substrat classique pour une technologie CMOS. La configuration de base est composée uniquement de trois transistors et d'une diode qui collecte par diffusion thermique la charge. Celle-ci est générée dans la couche épitaxiale mince, non-désertée en dessous du circuit de lecture. Cela permet d'obtenir un détecteur mince, de haute résolution, d'une surface entièrement sensible à la radiation et d'un faible coût de fabrication. Les simulations détaillées ont été effectuées en utilisant le logiciel ISE-TCAD pour étudier le mécanisme de collection de charge. Quatre prototypes ont été fabriqués en technologies CMOS submicroniques pour démontrer la viabilité de cette technique. Le gain des pixels a été calibré par irradiation à l'aide d'une source 55Fe et en appliquant la méthode fondée sur la séquence de Poisson. Les prototypes ont été également exposés aux faisceaux de particules de haute énergie au CERN. D'excellentes performances de détection ont été prouvées. Elles s'expriment par un rapport signal sur bruit supérieur à 30, une résolution spatiale de 1.5 μm et une efficacité de détection proche de 100%. Les tests d'irradiation ont démontré une résistance aux flux de neutrons jusqu'a quelques 1012 n/cm2 et une résistance aux rayonnements ionisants jusqu'à quelques centaines kRad. Des idées futures telles que l'amplification du signal sur le pixel, le double échantillonnage ainsi que la conception d'un pixel en mode courrant ont été également présentées

    Monolithic Pixel Detectors in a Deep Submicron SOI Process

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    Abstract A compact charge-signal processing chain, composed of a two-stage semi-gaussian preamplifier-signal shaping filter, a discriminator and a binary counter, implemented in a prototype pixel detector using 0.20 ÎĽm CMOS Silicon on Insulator process, is presented. The gain of the analog chain was measured 0.76 V/fC at the signal peaking time about 300 ns and the equivalent noise charge referred to the input of 80 e -

    Asynchronous Approximation of a Center of Gravity for Pixel Detectors’ Readout Circuits

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    New Generation of Monolithic Active Pixel Sensors for Charged Particle Detection

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    STRASBOURG-Sc. et Techniques (674822102) / SudocSudocFranceF

    Vertically Integrated Circuits at Fermilab

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    The exploration of the vertically integrated circuits, also commonly known as 3D-IC technology, for applications in radiation detection started at Fermilab in 2006. This paper examines the opportunities that vertical integration offers by looking at various 3D designs that have been completed by Fermilab. The emphasis is on opportunities that are presented by through silicon vias (TSV), wafer and circuit thinning and finally fusion bonding techniques to replace conventional bump bonding. Early work by Fermilab has led to an international consortium for the development of 3D-IC circuits for High Energy Physics. The consortium has submitted over 25 different designs for the Fermilab organized MPW run organized for the first time

    Multi-Vdd Design for Content Addressable Memories (CAM): A Power-Delay Optimization Analysis

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    In this paper, we characterize the interplay between power consumption and performance of a matchline-based Content Addressable Memory and then propose the use of a multi-Vdd design to save power and increase post-fabrication tunability. Exploration of the power consumption behavior of a CAM chip shows the drastically different behavior among the components and suggests the use of different and independent power supplies. The complete design, simulation and testing of a multi-Vdd CAM chip along with an exploration of the multi-Vdd design space are presented. Our analysis has been applied to simulated models on two different technology nodes (130 nm and 45 nm), followed by experiments on a 246-kb test chip fabricated in 130 nm Global Foundries Low Power CMOS technology. The proposed design, operating at an optimal operating point in a triple-Vdd configuration, increases the power-delay operation range by 2.4 times and consumes 25.3% less dynamic power when compared to a conventional single-Vdd design operating over the same voltage range with equivalent noise margin. Our multi-Vdd design also helps save 51.3% standby power. Measurement results from the test chip combined with the simulation analysis at the two nodes validate our thesis