419 research outputs found

    Accesorios para vehículos Marcali S.A.

    Get PDF
    En el momento que se venda en vehículo el cliente pasa por el asesor comercial de ventas escoge el carro que necesita y después pasa el asesor comercial de accesorios; en el momento se da la necesidad de comprar accesorios de seguridad ya que algunos artículos como las lunas, lamevidrios y llantas están dispuestos a que los roben, otros artículos como seguro de pernos y películas de seguridad son necesarios para la seguridad del cliente. De otro lado los productos relacionados con centro de entretenimiento, tapicería en cuero, techos eléctricos, GPS, spoiler, estribos, farolas entre otros, son accesorios que personalizan los carros y hace que el cliente escoge como quiere ver su vehículo nuevo. En este documento se plantea varias ideas con el fin de tener en cuenta los accesorios en la venta de automóvil donde se beneficiaran tanto como el vendedor comercial como Marcali; es importante resaltar que la mano de obra y la fuerza de ventas de accesorios se maneja por un outsourcing donde el porcentaje dela mano de obra y la comisión se le suma al valor de los artículos, también se manejara una políticas que se van a plantear en el proyecto con el fin de manejar de una manera más directa los accesorios y que no tengan mucha independencia el outsourcing. En el tema de los inventarios es muy importante ya que se ve problemas en la hora de entrega, en el manejo de las referencias y pedidos, el lugar de almacenamiento y la facturación de este; se propone un manejo más centralizado y sistemático con el fin de agilizar los procesos que se manejan actualmente sean más eficientes y que los errores no se vean perjudicados al cliente final.Desarrollo. Mercado de Accesorios. Investigación de Mercados. Marcas. Kia. Renault. Mercedes-Benz. CJD (Jeep, Dodge y Ram). Proceso de Accesorios.Administrador de EmpresasPregrad

    Fast and compact evolvable systolic arrays on dynamically reconfigurable FPGAs

    Get PDF
    Evolvable hardware may be considered as the result of a design methodology that employs an evolutionary algorithm to find an optimal solution to a given problem in the form of a digital circuit. Evolutionary algorithms typically require testing thousands of candidate solutions, taking long time to complete. It would be desirable to reduce this time to a few seconds for applications that require a fast adaptation to a problem. Also, it is important to consider architectures that may operate at high clock speeds in order to reach very speed-demanding situations. This paper presents an implementation on an FPGA of an evolvable hardware image filter based on a systolic array architecture that uses dynamic partial reconfiguration in order to change between different candidate solutions. The neighbor to neighbor connections of the array offer improved performance versus other approaches, like Cartesian Genetic Programming derived circuits. Time savings due to faster evaluation compensate the slower reconfiguration time compared with virtual reconfiguration approaches, but, at any rate, reconfiguration time has been improved also by reducing the elements to reconfigure to just the LUT contents of the configurable blocks. The techniques presented in this paper lead to circuits that may operate at up to 500 MHz (in a Virtex-5), filtering 500 megapixels per second, the processing element size of the array is reduced to 2 CLBs, and over 80000 evaluations per second in a multiplearray structure in an FPGA permit to obtain good quality filters in around 3 seconds of evolution time

    Active learning methodologies at the university classroom

    Full text link
    [EN] This paper identifies a set of active learning methodologies, which have in common the consideration of the emotion as a key element for learning. Active learning methodologies are not only intended to awaken emotions but also taught with emotion (Sempere-Ripoll and Rodriguez-Villalobos, 2019). To this extent, different teaching methodologies are used that complement each other, leading to reinforce and consolidate learning. Accordingly, the main aim of this work is to review the different active learning methodologies that can be applied at the university classroom.The authors acknowledge the support from the Universitat Polit√®cnica de Val√®ncia (UPV) through the Projects of Innovation and Educational Improvement ¬ŅLa docencia inversa como metodolog√≠a soporte a metodolog√≠as activas de aprendizaje¬Ņ (PIME/21-22/263) and ¬ŅInnovaci√≥n y mejora educativa aplicada a los Objetivos de Desarrollo Sostenible en la ETSII¬Ņ (PIME/21-22/281).Andres, B.; Sempere-Ripoll, F.; Esteso, A.; Torre-Mart√≠nez, MRDL. (2022). Active learning methodologies at the university classroom. EDULEARN Proceedings (Internet). 2927-2935. https://doi.org/10.21125/edulearn.2022.07402927293

    A scalable evolvable hardware processing array

    Get PDF
    Evolvable hardware (EH) is an interesting alternative to conventional digital circuit design, since autonomous generation of solutions for a given task permits self-adaptivity of the system to changing environments, and they present inherent fault tolerance when evolution is intrinsically performed. Systems based on FPGAs that use Dynamic and Partial Reconfiguration (DPR) for evolving the circuit are an example. Also, thanks to DPR, these systems can be provided with scalability, a feature that allows a system to change the number of allocated resources at run-time in order to vary some feature, such as performance. The combination of both aspects leads to scalable evolvable hardware (SEH), which changes in size as an extra degree of freedom when trying to achieve the optimal solution by means of evolution. The main contributions of this paper are an architecture of a scalable and evolvable hardware processing array system, some preliminary evolution strategies which take scalability into consideration, and to show in the experimental results the benefits of combined evolution and scalability. A digital image filtering application is used as use case

    Structure, Atomistic Simulations, and Phase Transition of Stoichiometric Yeelimite

    Get PDF
    ABSTRACT: Yeelimite, Ca4[Al6O12]SO4, is outstanding as an aluminate sodalite, being the framework of these type of materials flexible and dependent on ion sizes and anion ordering/disordering. On the other hand, yeelimite is also important from an applied perspective as it is the most important phase in calcium sulfoaluminate cements. However, its crystal structure is not well studied. Here, we characterize the room temperature crystal structure of stoichiometric yeelimite through joint Rietveld refinement using neutron and Xray powder diffraction data coupled with chemical soft-constraints. Our structural study shows that yeelimite has a lower symmetry than that of the previously reported tetragonal system, which we establish to likely be the acentric orthorhombic space group Pcc2, with a ‚ąö2a √ó ‚ąö2a √ó a superstructure based on the cubic sodalite structure. Final unit cell values were a = 13.0356(7) √Ö, b = 13.0350(7) √Ö, and c = 9.1677(2) √Ö. We determine several structures using density functional theory calculations, with the lowest energy structure being Pcc2 in agreement with our experimental result. Yeelimite undergoes a reversible phase transition to a higher-symmetry phase which has been characterized to occur at 470 ¬įC by thermodiffractometry. The higher-symmetry phase is likely cubic or pseudocubic possessing an incommensurate superstructure, as suggested by our theoretical calculations which show a phase transition from an orthorhombic to a tetragonal structure. Our theoretical study also predicts a pressure-induced phase transition to a cubic structure of space group I43m. Finally, we show that our reported crystal structure of yeelimite enables better mineralogical phase analysis of commercial calcium sulfoaluminate cements, as shown by RF values for this phase, 6.9% and 4.8% for the previously published orthorhombic structure and for the one reported in this study, respectively.Universidad de M√°laga. Campus de Excelencia Internacional. Andaluc√≠a Tech

    Noise-agnostic adaptive image filtering without training references on an evolvable hardware platform

    Get PDF
    One of the main concerns of evolvable and adaptive systems is the need of a training mechanism, which is normally done by using a training reference and a test input. The fitness function to be optimized during the evolution (training) phase is obtained by comparing the output of the candidate systems against the reference. The adaptivity that this type of systems may provide by re-evolving during operation is especially important for applications with runtime variable conditions. However, fully automated self-adaptivity poses additional problems. For instance, in some cases, it is not possible to have such reference, because the changes in the environment conditions are unknown, so it becomes difficult to autonomously identify which problem requires to be solved, and hence, what conditions should be representative for an adequate re-evolution. In this paper, a solution to solve this dependency is presented and analyzed. The system consists of an image filter application mapped on an evolvable hardware platform, able to evolve using two consecutive frames from a camera as both test and reference images. The system is entirely mapped in an FPGA, and native dynamic and partial reconfiguration is used for evolution. It is also shown that using such images, both of them being noisy, as input and reference images in the evolution phase of the system is equivalent or even better than evolving the filter with offline images. The combination of both techniques results in the completely autonomous, noise type/level agnostic filtering system without reference image requirement described along the paper

    Sophisticated security verification on routing repaired balanced cell-based dual-rail logic against side channel analysis

    Get PDF
    Conventional dual-rail precharge logic suffers from difficult implementations of dual-rail structure for obtaining strict compensation between the counterpart rails. As a light-weight and high-speed dual-rail style, balanced cell-based dual-rail logic (BCDL) uses synchronised compound gates with global precharge signal to provide high resistance against differential power or electromagnetic analyses. BCDL can be realised from generic field programmable gate array (FPGA) design flows with constraints. However, routings still exist as concerns because of the deficient flexibility on routing control, which unfavourably results in bias between complementary nets in security-sensitive parts. In this article, based on a routing repair technique, novel verifications towards routing effect are presented. An 8 bit simplified advanced encryption processing (AES)-co-processor is executed that is constructed on block random access memory (RAM)-based BCDL in Xilinx Virtex-5 FPGAs. Since imbalanced routing are major defects in BCDL, the authors can rule out other influences and fairly quantify the security variants. A series of asymptotic correlation electromagnetic (EM) analyses are launched towards a group of circuits with consecutive routing schemes to be able to verify routing impact on side channel analyses. After repairing the non-identical routings, Mutual information analyses are executed to further validate the concrete security increase obtained from identical routing pairs in BCDL

    Nitrene-carbene-carbene rearrangement. photolysis and thermolysis of tetrazolo[5,1- a ]phthalazine with formation of 1-phthalazinylnitrene, o-cyanophenylcarbene, and phenylcyanocarbene

    Get PDF
    1-Azidophthalazine 9A is generated in trace amount by mild FVT of tetrazolo[5,1-a]phthalazine 9T and is observable by its absorption at 2121 cm-1 in the Ar matrix IR spectrum. Ar matrix photolysis of 9T/9A at 254 nm causes ring opening to generate two conformers of (o-cyanophenyl) diazomethane 11 (2079 and 2075 cm-1), followed by (o-cyanophenyl)carbene 312, cyanocycloheptatetraene 13, and finally cyano(phenyl)carbene 314 as evaluated by IR spectroscopy. The two carbenes 312 and 314 were observed by ESR spectroscopy (D|hc = 0.5078, E|hc = 0.0236 and D|hc = 0.6488, E|hc = 0.0195 cm-1, respectively). The rearrangement of 12 √Ę., 13 √Ę., 14 constitutes a carbene-carbene rearrangement. 1-Phthalazinylnitrene 310 is observed by means of its UV-vis spectrum in Ar matrix following FVT of 9 above 550 C. Rearrangement to cyanophenylcarbenes also takes place on FVT of 9 as evidenced by observation of the products of ring contraction, viz., fulvenallenes and ethynylcyclopentadienes 16-18. Thus the overall rearrangement 10 ‚Üí 11 ‚Üí 12 √Ę., 13 √Ę., 14 can be formulated

    A self-adaptive image processing application based on evolvable and scalable hardware

    Full text link
    Evolvable Hardware (EH) is a technique that consists of using reconfigurable hardware devices whose configuration is controlled by an Evolutionary Algorithm (EA). Our system consists of a fully-FPGA implemented scalable EH platform, where the Reconfigurable processing Core (RC) can adaptively increase or decrease in size. Figure 1 shows the architecture of the proposed System-on-Programmable-Chip (SoPC), consisting of a MicroBlaze processor responsible of controlling the whole system operation, a Reconfiguration Engine (RE), and a Reconfigurable processing Core which is able to change its size in both height and width. This system is used to implement image filters, which are generated autonomously thanks to the evolutionary process. The system is complemented with a camera that enables the usage of the platform for real time applications

    Cost and energy efficient reconfigurable embedded platform using Spartan-6 FPGAs

    Get PDF
    Modern FPGAs with run-time reconfiguration allow the implementation of complex systems offering both the flexibility of software-based solutions combined with the performance of hardware. This combination of characteristics, together with the development of new specific methodologies, make feasible to reach new points of the system design space, and make embedded systems built on these platforms acquire more and more importance. However, the practical exploitation of this technique in fields that traditionally have relied on resource restricted embedded systems, is mainly limited by strict power consumption requirements, the cost and the high dependence of DPR techniques with the specific features of the device technology underneath. In this work, we tackle the previously reported problems, designing a reconfigurable platform based on the low-cost and low-power consuming Spartan-6 FPGA family. The full process to develop the platform will be detailed in the paper from scratch. In addition, the implementation of the reconfiguration mechanism, including two profiles, is reported. The first profile is a low-area and low-speed reconfiguration engine based mainly on software functions running on the embedded processor, while the other one is a hardware version of the same engine, implemented in the FPGA logic. This reconfiguration hardware block has been originally designed to the Virtex-5 family, and its porting process will be also described in this work, facing the interoperability problem among different families
    • ‚Ķ
    corecore