35 research outputs found

    Hardware Design and Testing of the Generic Rear Transition Module for the Global Trigger Subsystem of ATLAS Phase-II Upgrade

    No full text
    In the framework of the ATLAS experiment’s Phase-II Upgrade at the High-Luminosity Large Hadron Collider (HL-LHC), new and improved trigger hardware and algorithms will be implemented onto a single-level, 10 μs\mu s-latency architecture. The Global Trigger is a new subsystem which will bring event-filter capabilities by performing offline-like algorithms on full-granularity calorimeter data. The implementation of the functionality is firmware-focused and composed of several processing nodes, which are hosted on identical hardware, made up of an Advanced Telecommunications Computing Architecture (ATCA) front board, called Global Common Module (GCM), and a rear transition module (RTM), called Generic RTM (GRM). GRM, which was developed to mitigate the risks deriving from complex design and power management of GCM, features an advanced Xilinx Versal Prime system-on-chip and can handle communication with GCM and Front-End Link eXchange (FELIX) subsystem and trigger processors through 124 25. 8 Gb/s transceiver links, for readout and control. Additionally, GRM mounts a Low-Power GigaBit Transceiver (lpGBT) chip which enables emulation of the detector front-ends for integration tests. This article proceeds from the TWEPP 2022 conference and presents the GRM hardware design and the testing of its key functionalities

    TWEPP 2021 Topical Workshop on Electronics for Particle Physics

    No full text
    The HL-LHC will start operations in 2027, to deliver more than ten times the integrated luminosity of the LHC Runs 1-3 combined. Meeting these requirements poses significant challenges to the hardware design of the Trigger and Data Acquisition system. Global Trigger is a new subsystem, which will perform offline-like algorithms on full-granularity calorimeter data. The hardware implementation of the Global Trigger consists of three primary components: Multiplexer Processor layer, Global Event Processing layer, and demultiplexing Global-to-CTP Interface, all of which have identical hardware. The single Global Common Module hardware is implemented across the Global Trigger system

    Hardware Design and Testing of the Generic Rear Transition Module for the Global Trigger Subsystem of ATLAS Phase-II Upgrade

    No full text
    In the framework of the ATLAS experiment’s Phase-II Upgrade at the High-Luminosity Large Hadron Collider (HL-LHC), new and improved trigger hardware and algorithms will be implemented onto a single-level, 10 μs\mu s-latency architecture. The Global Trigger is a new subsystem which will bring event-filter capabilities by performing offline-like algorithms on full-granularity calorimeter data. The implementation of the functionality is firmware-focused and composed of several processing nodes, which are hosted on identical hardware, made up of an Advanced Telecommunications Computing Architecture (ATCA) front board, called Global Common Module (GCM), and a rear transition module (RTM), called Generic RTM (GRM). GRM, which was developed to mitigate the risks deriving from complex design and power management of GCM, features an advanced Xilinx Versal Prime system-on-chip and can handle communication with GCM and Front-End Link eXchange (FELIX) subsystem and trigger processors through 124 25. 8 Gb/s transceiver links, for readout and control. Additionally, GRM mounts a Low-Power GigaBit Transceiver (lpGBT) chip which enables emulation of the detector front-ends for integration tests. This article proceeds from the TWEPP 2022 conference and presents the GRM hardware design and the testing of its key functionalities

    Hardware Design and Testing of the Generic Rear Transition Module for the Global Trigger Subsystem of ATLAS Phase-II Upgrade

    No full text
    The High-Luminosity Large Hadron Collider (HL-LHC) will deliver more than ten times the integrated luminosity of the previous runs 1-3 combined. Meeting higher throughput requirements poses new challenges to the Trigger and Data Acquisition (TDAQ) systems of the LHC experiments. In the framework of the ATLAS experiment’s Phase-II Upgrade, new and improved trigger hardware and algorithms will be implemented onto a single-level, 10 μs\mu s-latency architecture. The Global Trigger is a new subsystem which will bring event-filter capabilities by performing offline-like algorithms on full-granularity calorimeter data. The implementation of the functionality is firmware-focused and composed of several processing nodes, which are hosted on identical hardware, called Global Common Module (GCM). GCM is an Advanced Telecommunications Computing Architecture front board. A matching rear-transition module (RTM), called Generic RTM (GRM) was also developed to mitigate the risks deriving from complex design and power management. GRM features an advanced Xilinx Versal Prime system-on-chip and can handle communication with the Front-End Link eXchange (FELIX) subsystem and trigger processors thought optical links, for readout and control. Additionally, GRM mounts a Low-Power GigaBit Transceiver (lpGBT) chip which enables emulation of the detector front-ends for integration tests. This summary presents the GRM hardware design and the testing of its key functionalities

    Prototype Hardware Design and Testing of the Global Common Module (GCM) for the Global Trigger subsystem of the ATLAS Phase-II Upgrade

    No full text
    The HL-LHC will start operations in 2027, to deliver more than ten times the integrated luminosity of the LHC Runs 1-3 combined. Meeting these requirements poses significant challenges to the hardware design of the Trigger and Data Acquisition system. Global Trigger is a new subsystem, which will perform offline-like algorithms on full-granularity calorimeter data. The hardware implementation of the Global Trigger consists of three primary components: Multiplexer Processor layer, Global Event Processing layer, and demultiplexing Global-to-CTP Interface, all of which have identical hardware. The single Global Common Module hardware is implemented across the Global Trigger system

    Prototype Hardware Design and Testing of the Global Common Module for the Global Trigger Subsystem of the ATLAS Phase-II Upgrade

    No full text
    The high-luminosity large hadron collider (HL-LHC) will deliver more than ten times the integrated luminosity of the previous runs combined. Meeting its stricter requirements poses significant challenges to the Trigger and Data Acquisition (TDAQ) systems of the LHC experiments. Introduced in the framework of the ATLAS experiment's Phase-II Upgrade, the Global Trigger (GT) is a new subsystem which will perform offline-like algorithms on full-granularity calorimeter data. The implementation of the GT's functionality is firmware-focused and is composed of three layers: Multiplexing (or Data Aggregating), Global Event Processing, and demultiplexing interface to the Central Trigger Processor. Each layer will be composed of several, similar nodes, and will be hosted on replicas of identical hardware, the Global Common Module (GCM), an ATCA front board which will be adopted throughout the entire GT subsystem. This article proceeds from the TWEPP 2021 conference and presents the GCM hardware design, performed in 2020, and focuses on the results of its extensive testing performed in 2021

    The Prototype Hardware Design and Test of Global Common Module for Global Trigger System of the ATLAS Phase II Upgrade

    No full text
    The HL-LHC [1] is expected to start operations in the middle of 2027, to deliver more than ten times the integrated luminosity of the LHC Runs 1-3 combined (up to 4000 fb−1). Meeting these requirements poses significant challenges to the hardware design of Trigger and Data Acquisition system. A baseline architecture, based on a single-level hardware trigger with a maximum rate of 1 MHz and 10 µs latency, is proposed for ATLAS. The hardware-based Level-0 Trigger system is composed of the Level-0 Calorimeter Trigger (L0Calo) [2], the Level-0 Muon Trigger (L0Muon) [3], the Global Trigger [4] and the Central Trigger sub-systems [4]. The Global Trigger is a new subsystem, which will perform offline-like algorithms on full-granularity calorimeter data. The calorimeter detector subsystems, FEXs [3], and MUCTPI [3] provide serial data for each bunch crossing to the MUX layer. These signals are then time-multiplexed [5] and the signals for a given event are transported to a single GEP node that executes the algorithms. The results are then sent to the CTP through the CTP Interface. The hardware implementation of the Global Trigger consists of three primary components: a Multiplexer Processor (MUX) layer, a GEP layer, and a demultiplexing Global-to-CTP Interface (CTP Interface), all of which have identical hardware composed of ATCA modules and FPGAs with many multi-gigabit transceivers. The single Global Common Module (GCM) hardware is implemented across the Global Trigger system, minimizing the complexity of the firmware and simplifying the system design and long-term maintenance

    Hardware Design of the Generic Rear Transition Module for the Global Trigger System of the ATLAS Phase II Upgrade

    No full text
    The High-Luminosity Large Hadron Collider (HL-LHC) is expected to start operations in the middle of 2027, to deliver more than ten times the integrated luminosity of the LHC Runs 1-3 combined (up to 4000 fb−1). Meeting these requirements poses significant challenges to the hardware design of the Trigger and Data Acquisition (TDAQ) system. Global Trigger is a new subsystem in the ATLAS Phase-II upgrade, which will bring event filter-like capability to the Level-0 trigger system. A common hardware platform in Advanced Telecommunications Computing Architecture (ATCA) form factor named Global Common Module (GCM) is proposed to be configured as processor nodes in the Global Trigger. To mitigate the risk and simplify the GCM hardware design, a Generic Rear Transition Module (GRM) is being developed. GRM, which has been implemented with a Xilinx Versal Prime FPGA and sufficient multi-gigabit transceivers, aims at system control and communication with the Front-End Link eXchange (FELIX). It could also provide additional processing or readout capacity

    Multiplexing Firmware Prototypes for the Global Trigger System of the ATLAS Phase-II Upgrade

    No full text
    The Global Trigger will be introduced in the ATLAS experiment Phase-II Trigger Upgrade to evaluate data from all sub-detectors at every bunch-crossing. This requires the handling of data with different rates, latencies and protocols. Different flavors of firmware will be developed to time-multiplex and aggregate data within an event, from up to 72 input optical channels per instance, and to convey that data to one of the Global Event Processor nodes to process that particular event

    The Prototype Hardware Design of Global Common Module for Global Trigger System of the ATLAS Phase-II Upgrade on HL-LHC

    No full text
    The HL-LHC [1] is expected to start operations in the middle of 2027, to deliver more than ten times the integrated luminosity of the LHC Runs 1-3 combined (up to 4000 fb−1). Meeting these requirements poses significant challenges to the hardware design of Trigger and Data Acquisition system. A baseline architecture, based on a single-level hardware trigger with a maximum rate of 1 MHz and 10 µs latency, is proposed for ATLAS. The hardware-based Level-0 Trigger system is composed of the Level-0 Calorimeter Trigger (L0Calo) [2], the Level-0 Muon Trigger (L0Muon) [3], the Global Trigger [4] and the Central Trigger sub-systems [4]. The Global Trigger is a new subsystem, which will perform offline-like algorithms on full-granularity calorimeter data. The calorimeter detector subsystems, FEXs [3], and MUCTPI [3] provide serial data for each bunch crossing to the MUX layer. These signals are then time-multiplexed [5] and the signals for a given event are transported to a single GEP node that executes the algorithms. The results are then sent to the CTP through the CTP Interface. The hardware implementation of the Global Trigger consists of three primary components: a Multiplexer Processor (MUX) layer, a GEP layer, and a demultiplexing Global-to-CTP Interface (CTP Interface), all of which have identical hardware composed of ATCA modules and FPGAs with many multi-gigabit transceivers. The single Global Common Module (GCM) hardware is implemented across the Global Trigger system, minimizing the complexity of the firmware and simplifying the system design and long-term maintenance
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