New Figure-of-Merit Combining Semiconductor and Multi-Level Converter Properties

Figures-of-Merit (FOMs) are widely-used to compare power semiconductor materials and devices and to motivate research and development of new technology nodes. These material- and device-specific FOMs, however, fail to directly translate into quantifiable performance in a specific power electronics application. Here, we combine device performance with specific bridge-leg topologies to propose the extended FOM, or X-FOM, a Figure-of-Merit that quantifies bridge-leg performance in multi-level (ML) topologies and supports the quantitative comparison and optimization of topologies and power devices. To arrive at the proposed X-FOM, we revisit the fundamental scaling laws of the on-state resistance and output capacitance of power semiconductors to first propose a revised device-level semiconductor Figure-of-Merit (D-FOM). The D-FOM is then generalized to a multi-level topology with an arbitrary number of levels, output power, and input voltage, resulting in the X-FOM that quantitatively compares hard-switched semiconductor stage losses and filter stage requirements across different bridge-leg structures and numbers of levels, identifies the maximum achievable efficiency of the semiconductor stage, and determines the loss-optimal combination of semiconductor die area and switching frequency. To validate the new X-FOM and showcase its utility, we perform a case study on candidate bridge-leg structures for a three-phase 10 kW photovoltaic (PV) inverter, with the X-FOM showing that (a) the minimum hard-switching losses are an accurate approximation to predict the theoretically maximum achievable efficiency and relative performance between bridge-legs and (b) the 3-level bridge-leg outperforms the 2-level configuration, despite utilizing a SiC MOSFET with a lower D-FOM than in the 2-level case.ISSN:2644-131

Novel Motor-Kinetic-Energy-Based Power Pulsation Buffer Concept for Single-Phase-Input Electrolytic-Capacitor-Less Motor-Integrated Inverter System

The motor integration of singe-phase-supplied Variable-Speed Drives (VSDs) is prevented by the significant volume, short lifetime, and operating temperature limit of the electrolytic capacitors required to buffer the pulsating power grid. The DC-link energy storage requirement is eliminated by using the kinetic energy of the motor as a buffer. The proposed concept is called the Motor-Integrated Power Pulsation Buffer (MPPB), and a control technique and structure are detailed that meet the requirements for nominal and faulted operation with a simple reconfiguration of existing controller blocks. A 7.5 kW, motor-integrated hardware demonstrator validated the proposed MPPB concept and loss models for a scroll compressor drive used in auxiliary railway applications. The MPPB drive with a front-end CISPR 11/Class A EMI filter, PFC rectifier stage, and output-side inverter stage achieved a power density of 0.91 kW L−1 (15 W in−3). The grid-to-motor-shaft efficiency exceeded 90% for all loads over 5 kW or 66% of nominal load, with a worst-case loss penalty over a conventional system of only 17%.ISSN:2079-929

The Impact of Multi-MHz Switching Frequencies on Dynamic On-Resistance in GaN-on-Si HEMTs

Dynamic on-resistance (dR on ), where the on-resistance immediately after turn-on is higher than the DC resistance, increases the conduction losses in power converters with gallium nitride high-electron-mobility transistors (GaN HEMTs). There exist no direct dR on measurements in the literature above 1 MHz, leaving designers unable to predict conduction losses in emerging multi-MHz applications. We address this literature gap by collecting the first on-state voltage dR on measurements at multi-MHz frequencies, with a focus on the zero-voltage-switching conditions that are predominantly employed at high frequency. On the selected commercially-available HEMT with a breakdown voltage below 200 V, the dynamic contribution asymptotes above ≈ 2 MHz, a finding predicted by the slow time constants of the traps that cause dR on . For the tested HEMT, we find a maximum dR on increase over the DC resistance of 2× in a multi-MHz, zero-voltage-switched application.ISSN:2644-131

Analytical Loss Model for Three-Phase 1200V SiC MOSFET Inverter Drive System Utilizing Miller Capacitor-Based dv/dt-Limitation

ISSN:2644-131

Conceptualization and Analysis of a Next-Generation Ultra-Compact 1.5-kW PCB-Integrated Wide-Input-Voltage-Range 12V-Output Industrial DC/DC Converter Module

The next-generation industrial environment requires power supplies that are compact, efficient, low-cost, and ultra-reliable, even across mains failures, to power mission-critical electrified processes. Hold-up time requirements and the demand for ultra-high power density and minimum production costs, in particular, drive the need for power converters with (i) a wide input voltage range, to reduce the size of the hold-up capacitor, (ii) soft-switching over the full input voltage and load ranges, to achieve low losses that facilitate a compact realization, and (iii) complete PCB-integration for low-cost manufacturing. In this work, we conceptualize, design, model, fabricate, and characterize a 1.5 kW, 12 V-output DC/DC converter for industrial power supplies that is required to operate across a wide 300 V–430 V input voltage range. This module utilizes an LLC-based control scheme for complete soft-switching and a snake-core transformer to divide the output current with a balanced flux among multiple secondary windings. Detailed loss models are derived for every component in the converter. The converter achieves close to 96% peak efficiency with a power density of 337 W in−3 (20.6 kW/dm−3), excellent matching to the derived loss models, and zero-voltage switching even down to zero load. The loss models are used to identify improvements to further boost efficiency, the most important of which is the minimization of delay times in synchronous rectification, and a subsequent improved 1.5 kW hardware module eliminates nearly 25% of converter losses for a peak efficiency of nearly 97% with a power density of 308 W in−3 (18.8 kW dm−3). Two 1.5 kW modules are then paralleled to achieve 3 kW output power at 12 V and 345 W in−3 (21.1 kW dm−3) with ideal current sharing between the secondary outputs and no drop in efficiency from a single module, an important characteristic enabled by the novel snake-core transformer.ISSN:2079-929

Novel ZVS S-TCM Modulation of Three-Phase AC/DC Converters

For three-phase AC-DC power conversion, the widely-used continuous current mode (CCM) modulation scheme results in relatively high semiconductor losses from hard-switching each device during half of the mains cycle. Triangular current mode (TCM) modulation, where the inductor current reverses polarity before turn-off, achieves zero-voltage-switching (ZVS) but at the expense of a wide switching frequency variation (15× for the three-phase design considered here), complicating filter design and compliance with EMI regulations. In this paper, we propose a new modulation scheme, sinusoidal triangular current mode (S-TCM), that achieves soft-switching, keeps the maximum switching frequency below the 150 kHz EMI regulatory band, and limits the switching frequency variation to only 3×. Under S-TCM, three specific modulation schemes are analyzed, and a loss-optimized weighting of the current bands across load is identified. The 2.2 kW S-TCM phase-leg hardware demonstrator achieves 99.7% semiconductor efficiency, with the semiconductor losses accurately analytically estimated within 10% (0.3 W). Relative to a CCM design, the required filter inductance is 6× lower, the inductor volume is 37% smaller, and the semiconductor losses are 55% smaller for a simultaneous improvement in power density and efficiency.ISSN:2644-131