Effects of annealing gas species on the electrical properties and reliability of Ge MOS capacitors with high-k Y 2O 3 gate dielectric

In this work, Ge MOS capacitors with Y 2O 3 gate dielectric were fabricated. The effects of annealing in N 2, NH 3 O 2 or NO ambient were investigated. Experimental results demonstrated that the NO annealing could improve both electrical properties and reliability of Ge MOS devices with Y 2O 3 dielectric. On the other hand, the NH 3 annealing resulted in H-related traps while the O 2 annealing suffered from extra GeO x growth, thus both degrading the performance of the devices. ©2009 IEEE.published_or_final_versionThe IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC 2009), Xi'an, China, 25-27 December 2009. In Proceedings of EDSSC, 2009, p. 243-24

Impacts of Ti on electrical properties of Ge metal-oxide-semiconductor capacitors with ultrathin high-κ LaTiON gate dielectric

Ge Metal-Oxide-Semiconductor (MOS) capacitors with LaON gate dielectric incorporating different Ti contents are fabricated and their electrical properties are measured and compared. It is found that Ti incorporation can increase the dielectric permittivity, and the higher the Ti content, the larger is the permittivity. However, the interfacial and gate-leakage properties become poorer as the Ti content increases. Therefore, optimization of Ti content is important in order to obtain a good trade-off among the electrical properties of the device. For the studied range of the Ti/La 2O 3 ratio, a suitable Ti/La 2O 3 ratio of 14.7% results in a high relative permittivity of 24.6, low interfacestate density of 3.1 × 10 11 eV -1 cm -2, and relatively low gate-leakage current density of 2.0×10 -3 Acm -2 at a gate voltage of 1 V. © The Author(s) 2010.published_or_final_versionSpringer Open Choice, 21 Feb 201

Improved properties of Ge MOS capacitors with HfTiON or HfTiO gate dielectric by using wet-NO ge-surface pretreatment

HfTiO/GeOxNy and HfTiON/GeOxNy stack gate dielectrics are prepared by using wet-NO or wet-N2O pretreatment on Ge substrate. Experimental results show that the wet NO pretreatment can lead to excellent interface properties, gate leakage properties and device reliability, especially for the HfTiON/GeOxNy dielectric. The involved mechanisms lie in the roles of N in blocking oxygen diffusion and Ge out-diffusion and suitable N incorporation in the GeO xNy interlayer, which effectively suppress further growth of GeOxNy interlayer and the growth of unstable GeO x during subsequent processing. © 2008 IEEE.published_or_final_versio

Suppressed growth of unstable low-fr GeOx interlayer in Ge metal-oxide-semiconductor capacitor with high-k gate dielectric by annealing in water vapor

The effects of water vapor added in the N2 annealing of high-k HfTiON gate dielectric on Ge metal-oxide-semiconductor capacitor are investigated. Both transmission-electron microscopy and ellipsometry indicate that, as compared to dry-N2 annealing, the wet-N2 annealing can greatly suppress the growth of unstable low-k GeOx at the dielectric/Ge interface, thus resulting in smaller equivalent dielectric thickness, as well as less interface states and dielectric charges. All these are attributed to the hydrolyzable property of GeOx in water. Moreover, the wet-N2 annealed capacitor has ten times lower gate-leakage current due to its better dielectric morphology as confirmed by atomic force microscopy. © 2007 American Institute of Physics.published_or_final_versio

Enhanced performance of Si MOS capacitors with HfTaOxNy gate dielectric by using AlOxNy or TaOxNy interlayer

Si MOS capacitors with HfTa oxide and oxynitride as gate dielectric were fabricated. Moreover, AlOxNy or TaOxN y was used as the interlayer between HfTa oxynitride and Si substrate to improve the electrical quality of the capacitors. Experimental results showed that the HfTaOxNy capacitor with TaO xNy interlayer achieved better performance with larger capacitance and smaller leakage current than its counterpart with AlO xNy interlayer. © 2008 IEEE.published_or_final_versio

A compact threshold-voltage model of MOSFETs with stack high-k gate dielectric

In this paper, a compact threshold-voltage model is developed for stack high-k gate-dielectric MOSFET with a thin interiayer. The simulated results are in good agreement with 2-D simulations. The influences of k value of the interlayer on threshold behaviors are investigated in detail. A low-k interlayer can effectively improve the threshold-voltage behaviors. Furthermore, the ratio of low-k interiayer EOT (equivalent oxide thickness) to high-k layer EOT is optimized by considering both threshold-voltage roll-off and gate leakage current. ©2009 IEEE.published_or_final_versionThe IEEE International Conference of Electron Devices and Solid-State Circuits (EDSSC 2009), Xian, China, 25-27 December 2009. In Proceedings of EDSSC, 2009, p. 236-23

Optimization of N content for higk-k LaTiON gate dielectric of Ge MOS capacitor

Thin LaTiON gate dielectric is deposited on Ge (100) substrate by reactive co-sputtering of La 2O 3 and Ti targets under different Ar/N 2 ratios of 24/3, 24/6, 24/12, and 24/18, and their electrical properties are investigated and compared. Results show that the LaTiON gate-dielectric Ge MOS capacitor prepared at an Ar/N 2 ratio of 24/6 exhibits highest relative permittivity, smallest capacitance equivalent thickness, and best electrical characteristics, including low interface-state density, small C-V hysteresis and low gate leakage current. This is attributed to the fact that a suitable N content in LaTiON can effectively suppress the growth of low-k GeO x interfacial layer between LaTiON and Ge substrate.published_or_final_versionThe IEEE International Conference of Electron Devices and Solid-State Circuits (EDSSC) 2009, Xi'an, China, 25-27 December 2009. In Proceedings of EDSSC, 2009, p. 225-22

Improved electrical properties of Ge p-MOSFET with HfO 2 gate dielectric by using TaO xN y interlayer

The electrical characteristics of germanium p-metal-oxide-semiconductor (p-MOS) capacitor and p-MOS field-effect transistor (FET) with a stack gate dielectric of HfO 2TaO xN y are investigated. Experimental results show that MOS devices exhibit much lower gate leakage current than MOS devices with only HfO 2 as gate dielectric, good interface properties, good transistor characteristics, and about 1.7-fold hole-mobility enhancement as compared with conventional Si p-MOSFETs. These demonstrate that forming an ultrathin passivation layer of TaO xN y on germanium surface prior to deposition of high- k dielectrics can effectively suppress the growth of unstable GeO x, thus reducing interface states and increasing carrier mobility in the inversion channel of Ge-based transistors. © 2008 IEEE.published_or_final_versio

Impacts of Ti content and annealing temperature on electrical properties of Si MOS capacitors with HfTiON gate dielectric

Proceedings of the IEEE International Conference of Electron Devices and Solid-State Circuits, 2009, p. 221-224HfTiON gate dielectric is fabricated by reactive co-sputtering method followed by annealing in N 2 ambient. The effects of Ti content and annealing temperature on the performances of HfTiON gate-dielectric Si MOS devices are investigated. Experimental results indicate that gate capacitance is increased with increasing Ti content. However, when the Ti/Hf ratio exceeds -1.75, increase of the gate capacitance becomes small. Surface roughness of the samples annealed at different temperatures is analyzed by AFM, and results show that high annealing temperature (e.g. 700 °C for 30 s) can produce smooth surface, thus resulting in low gate leakage current. ©2009 IEEE.published_or_final_versio

Comparative study of HfTa-based gate-dielectric Ge metal-oxide- semiconductor capacitors with and without AlON interlayer

The electrical properties and high-field reliability of HfTa-based gate-dielectric metal-oxide-semiconductor (MOS) devices with and without AlON interlayer on Ge substrate are investigated. Experimental results show that theMOS capacitor with HfTaON/AlON stack gate dielectric exhibits low interface-state/oxide-charge densities, low gate leakage, small capacitance equivalent thickness (∼1.1 nm), and high dielectric constant (∼20). All of these should be attributed to the blocking role of the ultrathin AlON interlayer against interdiffusions of Ge, Hf, and Ta and penetration of O into the Ge substrate, with the latter effectively suppressing the unintentional formation of unstable poorquality low-k GeO x and giving a superior AlON/Ge interface. Moreover, incorporation of N into both the interlayer and high-k dielectric further improves the device reliability under high-field stress through the formation of strong Nrelated bonds. © Springer-Verlag 2009.published_or_final_versionSpringer Open Choice, 01 Dec 201