Four point probe structures with buried electrodes for the electrical characterization of ultrathin conducting films

Test structures for the electrical characterization of ultrathin conductive (ALD) films are presented based on buried electrodes on which the ultrathin film is deposited.\ud This work includes test structure design and fabrication, and the electrical characterization of ALD TiN films down to 4 nm. It is shown that these structures can be used successfully to characterize sub 10 nm films.\u

Cross-Bridge Kelvin resistor structures for reliable measurement of low contact resistances and contact interface characterization

The parasitic factors that strongly influence the measurement accuracy of Cross-Bridge Kelvin Resistor (CBKR) structures for low specific contact resistances (rhoc) have been extensively discussed during last few decades and the minimum of the rhoc value, which could be accurately extracted, was estimated. We fabricated a set of various metal-to-metal CBKR structures with different geometries, i.e., shapes and dimensions, to confirm this limit experimentally and to create a method for contact metal-to-metal interface characterization. As a result, a model was developed to account for the actual current flow and a method for reliable rhoc extraction was created. This method allowed to characterize metal-to-metal contact interface. It was found that in the case of ideal metal-to-metal contacts, the measured CBKR contact resistance was determined by the dimensions of the two-metal stack in the area of contact and sheet resistances of the metals used

Metal contacts to lowly doped Si and ultra thin SOI

We present our investigations on the fabrication of ohmic and Schottky contacts of several metals on lowly doped bulk Si and SOI wafers. Through this paper we evaluate the fabrication of rectifying devices in which no doping is intentionally introduced

Fabrication and characterization of the charge-plasma diode

We present a new lateral Schottky-based rectifier called the charge-plasma diode realized on ultrathin silicon-oninsulator. The device utilizes the workfunction difference between two metal contacts, palladium and erbium, and the silicon body. We demonstrate that the proposed device provides a low and constant reverse leakage-current density of about 1 fA/μm with ON/OFF current ratios of around 107 at 1-V forward bias and room temperature. In the forward mode, a current swing of 88 mV/dec is obtained, which is reduced to 68 mV/dec by back-gate biasing

On the leakage problem of MIM capacitors due to improper etching of titanium nitride

In this work, Metal-insulator-metal (MIM) capacitor structures are fabricated in a technology using TiN as electrode material. The electrical characterization revealed devices with small and large leakage currents. Scanning Electron Microscopy (SEM) inspection showed a correlation between high leakage currents and large roughness in the dielectric layer of the capacitor. Cross-section of leaky capacitors by means of a Focussed Ion Beam (FIB) showed a rough edge of the bottom electrode and the presence of particles leading to a rough dielectric layer. These artefacts are the result of improper wet chemical etching of the TiN layer. It is shown, high leakage currents and improper etching of the TiN layer are correlated

Systematic TLM Measurements of NiSi and PtSi Specific Contact Resistance to n- and p-Type Si in a Broad Doping Range

We present the data on specific silicide-to-silicon contact resistance (ρc) obtained using optimized transmission-line model structures, processed for a broad range of various n- and p-type Si doping levels, with NiSi and PtSi as the silicides. These structures, despite being attractive candidates for embedding in the CMOS processes, have not been used for NiSi, which is the material of choice in modern technologies. In addition, no database for NiSi–silicon contact resistance exists, particularly for a broad range of doping levels. This letter provides such a database, using PtSi extensively studied earlier as a reference

Barrier properties of ALD W_1.55N thin films

W1.5N films grown by ALD from WF6, NH3, C2H4 and SiH4 as precursors were tested as Cu diffusion barriers in p+/n diodes and capacitors with SiO2 as a dielectric. I-V and C-V, C-t characteristics were measured before and after anneal. The layers exhibit excellent barrier properties against both Cu and Al interaction with silicon. No changes of current and capacitance attributed to a barrier failure were observed after annealing at 400°C. Samples without the barrier showed a drastic change of the I-V characteristics. The composition of the films was W1.5N as determined with RBS, being a mixture of WN and W2N phases The RMS- roughness was as low as 0.5-0.7 nm for a film with a thickness of 25 nm.</p

Low-temperature process steps for realization of non-volatile memory devices

In this work, the low-temperature process steps required for the realization of nano-crystal non-volatile memory cells are discussed. An amorphous silicon film, crystallized using a diode pumped solid state green laser irradiating at 532 nm, is proposed as an active layer. The deposition of the subsequent functional layers (e.g., gate oxide) can be done using CVD and ALD reactors in a cluster tool. We show that a high nanocrystal density (Si-NC), required for a good functionality of the memory device, can be obtained by using disilane (Si2H6) or trisilane (Si3H8, known as Silcore®) as precursors for LPCVD instead of silane, at a deposition temperature of 325 °C. The nanocrystals are encapsulated with an ALD-Al2O3 layer (deposited at 300 °C), which serves as oxidation barrier. The passivation of the realized structure is done with an ALD-TiN layer deposited at 425 °C. In this work, we realized Al/TiN/Al2O3/Si-NC/SiO2/Si(100) multilayer floating-gate structures, where the crystallized amorphous silicon film was for the time being replaced by a mono-crystalline silicon wafer, and the gate oxide was thermally grown instead of a low-temperature PECVD oxide. The structures were characterized in terms of their performance as memory cells. In addition, the feasibility to use laser crystallization for improving the amorphous silicon films (prior to the gate oxide deposition) was explored