SILC in MOS capacitors with poly-Si and poly-Si\u3csub\u3e0.7\u3c/sub\u3eGe\u3csub\u3e0.3\u3c/sub\u3e gate material

\u3cp\u3eIn this paper the DC-SILC characteristics of n\u3csup\u3e+\u3c/sup\u3e and p\u3csup\u3e+\u3c/sup\u3e poly-Si and poly-SiGe MOS capacitors are studied for substrate (+V\u3csub\u3eg\u3c/sub\u3e) and gate-injection (-V\u3csub\u3eg\u3c/sub\u3e) conditions. P\u3csup\u3e+\u3c/sup\u3e and n\u3csup\u3e+\u3c/sup\u3e-gates with poly silicon (poly-Si) and poly Silicon-Germanium (poly Si-\u3csub\u3e0.7\u3c/sub\u3eGe\u3csub\u3e0.3\u3c/sub\u3e) were used to study the influence of the gate workfunction on gate current and SILC currents. For n\u3csup\u3e+\u3c/sup\u3e poly-SiGe, reduced poly depletion and no significant difference in SILC characteristics compared to n\u3csup\u3e+\u3c/sup\u3e poly-Si gate devices is observed. For p\u3csup\u3e+\u3c/sup\u3e gate devices asymmetric SILC and reduced SILC for poly-SiGe is observed.\u3c/p\u3

Stress-induced leakage current in p\u3csup\u3e+\u3c/sup\u3e poly MOS capacitors with poly-Si and poly-Si\u3csub\u3e0.7\u3c/sub\u3eGe\u3csub\u3e0.3\u3c/sub\u3e gate material

\u3cp\u3eThe gate bias polarity dependence of stress-induced leakage current (SILC) of PMOS capacitors with a p\u3csup\u3e+\u3c/sup\u3e polycrystalline silicon (poly-Si) and polycrystalline Silicon-Germanium (poly-Si\u3csub\u3e0.7\u3c/sub\u3eGe\u3csub\u3e0.3\u3c/sub\u3e) gate on 5.6-nm thick gate oxides has been investigated. It is shown that the SILC characteristics are highly asymmetric with gate bias polarity. This asymmetric behavior is explained by the occurrence of a different injection mechanism for negative bias, compared to positive bias where Fowler-Nordheim (FN) tunneling is the main conduction mechanism. For gate injection, a larger oxide field is required to obtain the same tunneling current, which leads to reduced SILC at low fields. Moreover, at negative gate bias, the higher valence band position of poly-SiGe compared to poly-Si reduces the barrier height for tunneling to traps and hence leads to increased SILC. At positive gate bias, reduced SILC is observed for poly-SiGe gates compared to poly-Si gates. This is most likely due to a lower concentration of Boron in the dielectric in the case of poly-SiGe compared to poly-Si. This makes Boron-doped poly-SiGe a very interesting gate material for nonvolatile memory devices.\u3c/p\u3

New technique for measuring two-dimensional oxidation-enhanced diffusion in silicon at low temperatures

\u3cp\u3eIn this letter, a new high-resolution technique is presented for determining the lateral extent of oxidation-enhanced diffusion (OED). A periodic grid of lines and spacings is used as an oxidation mask. It will be shown that a simple secondary ion mass spectroscopy measurement permits the extraction of parameters in the lateral direction with a resolution which can be as good as 10 nm. The lateral extent of OED is depth dependent, consistent with a physical model of point-defect recombination at the Si/SiO\u3csub\u3e2\u3c/sub\u3e interface.\u3c/p\u3

A high-resolution study of two-dimensional oxidation-enhanced diffusion in silicon

\u3cp\u3eA new method for the determination of two-dimensional oxidation-enhanced diffusion (OED) is presented. The resolution of the technique in the lateral direction is ≈ 10 nm. The technique is used to study the influence of the gate reoxidation step on the channel profile of MOSFET's. For boron, it will be shown that the lateral extent of OED depends on the depth. The same technique is used to study segregation of boron during the lateral oxidation of the polysilicon gate.\u3c/p\u3

Effect of heating ramp rates on transient enhanced diffusion in ion-implanted silicon

\u3cp\u3eBoron marker-layer structures have been used to analyze the heating ramp-rate dependence of transient enhanced dopant diffusion (TED) during rapid thermal annealing of Si implantation damage. The study uses short anneals with heating ramp rates in the range 0.1-350°CVs, and peak temperatures in the range 900-1100°C. Increasing the ramp rate is found to reduce the amount of profile broadening caused by TED, as well as reducing the smaller amount of normal thermal-equilibrium diffusion which is related to thermal budget. The results show why high ramp rates lead to improved B-implant activation and junction-depth control in Si devices. An Ostwald ripening model of interstitial-cluster evolution describes the detailed trends in the data and predicts further improvements in the case of ultrarapid annealing.\u3c/p\u3