Application of compiler-assisted multiple instruction rollback recovery to speculative execution

Speculative execution is a method to increase instruction level parallelism which can be exploited by both super-scalar and VLIW architectures. The key to a successful general speculation strategy is a repair mechanism to handle mispredicted branches and accurate reporting of exceptions for speculated instructions. Multiple instruction rollback is a technique developed for recovery from transient processor failure. Many of the difficulties encountered during recovery from branch misprediction or from instruction re-execution due to exception in a speculative execution architecture are similar to those encountered during multiple instruction rollback. The applicability of a recently developed compiler-assisted multiple instruction rollback scheme to aid in speculative execution repair is investigated. Extensions to the compiler-assisted scheme to support branch and exception repair are presented along with performance measurements across ten application programs

Two-dimensional tetramer-cuprate Na5RbCu4(AsO4)4Cl2: phase transitions and AFMorder as seen by 87Rb NMR

We report the Rb nuclear magnetic resonance (NMR) results in a recently synthesized Na5RbCu4(AsO4)Cl2. This complex novel two-dimensional (2D) cuprate is an unique magnetic material, which contains layers of coupled Cu4O4 tetramers. In zero applied magnetic field, it orders antiferromagnetically via a second-order low-entropy phase transition at TN = 15(1) K. We characterise the ordered state by 87Rb NMR, and suggest for it a noncollinear rather than collinear arrangement of spins. We discuss the properties of Rb nuclear site and point out the new structural phase transition(s) around 74 K and 110 K.Comment: 2 pages, 2 figures, Proceedings of SCES'05, Vienna 200

Space Shuttle Communications Coverage Analysis for Thermal Tile Inspection

The space shuttle ultra-high frequency Space-to-Space Communication System has to provide adequate communication coverage for astronauts who are performing thermal tile inspection and repair on the underside of the space shuttle orbiter (SSO). Careful planning and quantitative assessment are necessary to ensure successful system operations and mission safety in this work environment. This study assesses communication systems performance for astronauts who are working in the underside, non-line-of-sight shadow region on the space shuttle. All of the space shuttle and International Space Station (ISS) transmitting antennas are blocked by the SSO structure. To ensure communication coverage at planned inspection worksites, the signal strength and link margin between the SSO/ISS antennas and the extravehicular activity astronauts, whose line-of-sight is blocked by vehicle structure, was analyzed. Investigations were performed using rigorous computational electromagnetic modeling techniques. Signal strength was obtained by computing the reflected and diffracted fields along the signal propagation paths between transmitting and receiving antennas. Radio frequency (RF) coverage was determined for thermal tile inspection and repair missions using the results of this computation. Analysis results from this paper are important in formulating the limits on reliable communication range and RF coverage at planned underside inspection and repair worksites

Array concepts for solid-state and vacuum microelectronics millimeter-wave generation

The authors have proposed that the increasing demand for contact watt-level coherent sources in the millimeter- and submillimeter-wave region can be satisfied by fabricating two-dimensional grids loaded with oscillators and multipliers for quasi-optical coherent spatial combining of the outputs of large numbers of low-power devices. This was first demonstrated through the successful fabrication of monolithic arrays with 2000 Schottky diodes. Watt-level power outputs were obtained in doubling to 66 GHz. In addition, a simple transmission-line model was verified with a quasi-optical reflectometer that measured the array impedance. This multiplier array work is being extended to novel tripler configurations using blocking barrier devices. The technique has also been extended to oscillator configurations where the grid structure is loaded with negative-resistance devices. This was first demonstrated using Gunn devices. More recently, a 25-element MESFET grid oscillating at 10 GHz exhibited power combining and self-locking. Currently, this approach is being extended to a 100-element monolithic array of Gunn diodes. This same approach should be applicable to planar vacuum electron devices such as the submillimeter-wave BWO (backward wave oscillator) and vacuum FET

Millimeter and submillimeter wave technology developments for the next generation of fusion devices

There is increasing demand for compact watt-level coherent sources in the millimeter and submillimeter wave region. The approach that we have taken to satisfy this need is to fabricate two-dimensional grids loaded with oscillators, electronic beam steerers, and frequency multipliers for quasioptical coherent spatial combining of the outputs of a large number of low-power devices

Exposing errors related to weak memory in GPU applications

© 2016 ACM.We present the systematic design of a testing environment that uses stressing and fuzzing to reveal errors in GPU applications that arise due to weak memory effects. We evaluate our approach on seven GPUS spanning three NVIDIA architectures, across ten CUDA applications that use fine-grained concurrency. Our results show that applications that rarely or never exhibit errors related to weak memory when executed natively can readily exhibit these errors when executed in our testing environment. Our testing environment also provides a means to help identify the root causes of such errors, and automatically suggests how to insert fences that harden an application against weak memory bugs. To understand the cost of GPU fences, we benchmark applications with fences provided by the hardening strategy as well as a more conservative, sound fencing strategy

GPU Concurrency: Weak Behaviours and Programming Assumptions

Concurrency is pervasive and perplexing, particularly on graphics processing units (GPUs). Current specifications of languages and hardware are inconclusive; thus programmers often rely on folklore assumptions when writing software. To remedy this state of affairs, we conducted a large empirical study of the concurrent behaviour of deployed GPUs. Armed with litmus tests (i.e. short concurrent programs), we questioned the assumptions in programming guides and vendor documentation about the guarantees provided by hardware. We developed a tool to generate thousands of litmus tests and run them under stressful workloads. We observed a litany of previously elusive weak behaviours, and exposed folklore beliefs about GPU programming---often supported by official tutorials---as false. As a way forward, we propose a model of Nvidia GPU hardware, which correctly models every behaviour witnessed in our experiments. The model is a variant of SPARC Relaxed Memory Order (RMO), structured following the GPU concurrency hierarchy

Compiler-assisted multiple instruction rollback recovery using a read buffer

Multiple instruction rollback (MIR) is a technique that has been implemented in mainframe computers to provide rapid recovery from transient processor failures. Hardware-based MIR designs eliminate rollback data hazards by providing data redundancy implemented in hardware. Compiler-based MIR designs have also been developed which remove rollback data hazards directly with data-flow transformations. This paper describes compiler-assisted techniques to achieve multiple instruction rollback recovery. We observe that some data hazards resulting from instruction rollback can be resolved efficiently by providing an operand read buffer while others are resolved more efficiently with compiler transformations. The compiler-assisted scheme presented consists of hardware that is less complex than shadow files, history files, history buffers, or delayed write buffers, while experimental evaluation indicates performance improvement over compiler-based schemes

Compiler-Assisted Signature Monitoring

Coordinated Science Laboratory was formerly known as Control Systems LaboratoryJoint Services Electronics Program / N00014-84-C-0149Office of Naval Research / N00014-88-K-0656National Science Foundation / MIP-8809478NCRNational Aeronautics and Space Administration / NASA NAG 1-61