Place branding and the Liverpool ’08 brand campaign in 'City of Liverpool'

Place branding brings together a range of existing specialisms, in particular those of brand management and development policy, to create a new discipline with equal emphasis on visionary strategy and hands-on implementation.1 Furthermore, Place branding ensures that the place gets due credit for its real strengths and positive behaviour, and that the place brand gains appropriate equity from the recognition, which that behaviour deserves

Current-Processing Current-Controlled Universal Biquad Filter

This paper presents a current-processing current-controlled universal biquad filter. The proposed filter employs only two current controlled current conveyor transconductance amplifiers (CCCCTAs) and two grounded capacitors. The proposed configuration can be used either as a single input three outputs (SITO) or as three inputs single output (TISO) filter. The circuit realizes all five different standard filter functions i.e. low-pass (LP), band-pass (BP), high-pass (HP), band-reject (BR) and all-pass (AP). The circuit enjoys electronic control of quality factor through the single bias current without disturbing pole frequency. Effects of non-idealities are also discussed. The circuit exhibits low active and passive sensitivity figures. The validity of proposed filter is verified through computer simulations using PSPICE

Place Pulling Power: a case of Liverpool’08

The paper contributes to the developing knowledge of place branding and highlights the importance of place branding strategies, that enabling the place to seek continual development and prosperity. The theoretical concepts of place brand creators, influencers and key driving forces, together with the different brand user groups are set against both current and historic indicators of place branding to model the pulling power of place branding. Interviews with key stakeholders indicate that, in the case of the Liverpool ’08 campaign, they are generally positive about the re-branding campaign and considered it to be creating a positive image that will continue to drive inward investment and increase tourism. However, it is clear that reputation and intangible factors are more important than functional and tangible factors when creating a positive brand image. Understanding place brands and the influence on the performance of the place, in terms of continuous development, regeneration and sustainability is important. Future comparative-case analyses between places that have gone through regeneration and repositioning could help to understand the significance of place branding, in terms of sustainability of place, and identify the specific facets of a place that could prove critical when putting place branding practices into action

Adiabatic Flip-Flops and Sequential Circuit Design using Novel Resettable Adiabatic Buffers

We propose novel resettable adiabatic buffers for five adiabatic logic families namely; Efficient Adiabatic Charge Recovery Logic (EACRL), Improved Efficient Charge Recovery Logic (IECRL), Positive Feedback Adiabatic Logic (PFAL), Complementary Pass-transistor Adiabatic Logic (CPAL) and Clocked Adiabatic Logic (CAL). We present the design of resettable flip-flops using the proposed buffers. The proposed flip-flops alleviate the problem of increased energy and area consumption incurred by the existing mux-based resettable flip-flops. We then design the 3-bit up-down counters and extended our comparison beyond energy dissipation using the above five adiabatic logic families. PFAL based sequential circuit designs gives the best performance trade-offs in terms of complexity, energy, speed and area compared to the other adiabatic designs

VHDL-based Modelling Approach for the Digital Simulation of 4-phase Adiabatic Logic Design

In comparison to conventional CMOS (non-adiabatic logic), the verification of the functionality and the low energy traits of adiabatic logic techniques are generally performed using transient simulations at the transistor level. However, as the size and complexity of the adiabatic system increases, the amount of time required to design and simulate also increases. Moreover, due to the complexity of synchronizing the power-clock phases, debugging of errors becomes difficult too thus, increasing the overall verification time. This paper proposes a VHSIC Hardware Descriptive Language (VHDL) based modelling approach for developing models representing the 4-phase adiabatic logic designs. Using the proposed approach, the functional errors can be detected and corrected at an early design stage so that when designing adiabatic circuits at the transistor level, the circuit performs correctly and the time for debugging the errors can substantially be reduced. The function defining the four periods of the trapezoidal AC power-clock is defined in a package which is followed by designing a library containing the behavioral VHDL models of adiabatic logic gates namely; AND/NAND, OR/NOR and XOR/XNOR. Finally, the model library is used to develop and verify the structural VHDL representation of the 4-phase 2-bit ring-counter and 3-bit up-down counter, as a design example that demonstrates the practicality of the proposed approach

Flux free growth of large FeSe1/2Te1/2 superconducting single crystals by an easy high temperature melt and slow cooling method

We report successful growth of flux free large single crystals of superconducting FeSe1/2Te1/2 with typical dimensions of up to few cm. The AC and DC magnetic measurements revealed the superconducting transition temperature (Tc) value of around 11.5K and the iso-thermal MH showed typical type-II superconducting behavior. The lower critical field being estimated by measuring the low field iso-thermal magnetization in superconducting regime is found to be above 200 Oe at 0K.Comment: 15 pages text + Figs. Novel large cm size FeSe1/2Te1/2 superconducting crystal

A VHDL-based Modelling Approach for Rapid Functional Simulation and Verification of Adiabatic Circuits

Adiabatic logic is an energy-efficient technique, however, the time required in the design, validation and debugging increases manifold for large-scale adiabatic system designs. In this endeavor, we present a Hardware Description Language (HDL) based modelling approach for 4-phase adiabatic logic design. The paper highlights the drawbacks of the existing approaches and proposes a new approach that captures the timing errors and detects the circuit’s invalid operation due to mutually exclusive inputs being violated. We develop a model library containing the function of the four periods used in the trapezoidal power-clock and the adiabatic logic gates. The validation and verification of the proposed approach were done on the ISO-14443 standard benchmark circuit, a 16-bit Cyclic Redundancy Check (CRC) circuit. The system modelled using HDL shows the timing agreement with the transistor-level SPICE simulations. The novel use of the four periods of a power-clock improves the robustness and reliability for the design and verification of large adiabatic systems

Modelling, Simulation and Verification of 4-phase Adiabatic Logic Design: A VHDL-Based Approach

The design and functional verification of the 4-phase adiabatic logic implementation take longer due to the complexity of synchronizing the power-clock phases. Additionally, as the adiabatic system scales, the amount of time in debugging errors increases, thus, increasing the overall design and verification time. This paper proposes a VHDL-based modelling approach for speeding up the design and verification time of the 4-phase adiabatic logic systems. The proposed approach can detect the functional errors, allowing the designer to correct them at an early design stage, leading to substantial reduction of the design and debugging time. The originality of this approach lies in the realization of the trapezoidal power-clock using function declaration for the four periods namely; Evaluation (E), Hold (H), Recovery (R) and Idle (I) exclusively. The four periods are defined in a VHDL package followed by a library design which contains the behavioral VHDL model of adiabatic NOT/BUF logic gate. Finally, this library is used to model and verify the structural VHDL representations of the 4-phase 2-bit ring-counter and 3-bit up-down counter, as design examples to demonstrate the practicality of the proposed approach

Energy efficient implementation of multi-phase quasi-adiabatic Cyclic Redundancy Check in near field communication

Ultra-low power operation in power-limited portable devices (e.g. cell phone and smartcard) is paramount. Existing conventional CMOS consume high energy. The adiabatic logic technique has the potential of rendering energy efficient operation. In this paper, a multi-phase quasi-adiabatic implementation of 16-bit Cyclic Redundancy Check (CRC) is proposed, compliant with the ISO/IEC-14443 standard for contactless smart cards. In terms of a number of CRC bits, the design is scalable and all generator polynomials and initial load values can be accommodated. The CRC design is used as a vehicle to evaluate a range of adiabatic logic styles and power-clock strategies. The effects of voltage scaling and variations in Process-Voltage-Temperature (PVT) are also investigated providing an insight into the robustness of adiabatic logic styles. PFAL and IECRL designs using a 4-phase power-clock are shown to be both the most energy-efficient and robust designs