174 research outputs found
ΠΡΡΠ΅ΠΊΡΠΈΠ²Π½ΠΎΡΡΡ ΠΈΡΠΏΠΎΠ»ΡΠ·ΠΎΠ²Π°Π½ΠΈΡ ΠΆΠΈΠ΄ΠΊΠΎΡΠ°Π·Π½ΡΡ ΠΎΠ³Π½Π΅ΡΡΡΠ°ΡΠΈΡ ΡΠΎΡΡΠ°Π²ΠΎΠ² Π½Π° ΠΎΠ±ΡΠ΅ΠΊΡΠ°Ρ ΡΠ½Π΅ΡΠ³Π΅ΡΠΈΠΊΠΈ
Π Π΄Π°Π½Π½ΠΎΠΉ ΡΡΠ°ΡΡΠ΅ ΡΠ°ΡΡΠΌΠ°ΡΡΠΈΠ²Π°Π΅ΡΡΡ ΠΈΡΠΏΠΎΠ»ΡΠ·ΠΎΠ²Π°Π½ΠΈΠ΅ ΡΡΡΠ΅ΡΡΠ²ΡΡΡΠΈΡ
ΠΎΠ³Π½Π΅ΡΡΡΠ°ΡΠΈΡ
ΡΠΎΡΡΠ°Π²ΠΎΠ². ΠΠΎΠ»Π΅Π΅ ΠΏΠΎΠ΄ΡΠΎΠ±Π½ΠΎ ΠΎΡΠ²Π΅ΡΠ°Π΅ΡΡΡ Π²ΠΎΠΏΡΠΎΡ ΠΏΡΠΈΠΌΠ΅Π½Π΅Π½ΠΈΡ ΠΆΠΈΠ΄ΠΊΠΎΡΠ°Π·Π½ΡΡ
ΠΎΠ³Π½Π΅ΡΡΡΠ°ΡΠΈΡ
ΡΠΎΡΡΠ°Π²ΠΎΠ² Π½Π° ΠΎΠ±ΡΠ΅ΠΊΡΠ°Ρ
ΡΠ½Π΅ΡΠ³Π΅ΡΠΈΠΊΠΈ, Π΄Π°Π΅ΡΡΡ ΠΈΡ
ΡΡΠ°Π²Π½ΠΈΡΠ΅Π»ΡΠ½ΡΠΉ Π°Π½Π°Π»ΠΈΠ·, ΠΈ ΠΏΠΎ ΡΠΎΠΎΡΠ²Π΅ΡΡΡΠ²ΡΡΡΠΈΠΌ ΠΊΡΠΈΡΠ΅ΡΠΈΡΠΌ ΠΎΡΠ΅Π½ΠΊΠΈ ΡΠ°ΠΊΠΈΡ
Π²Π΅ΡΠ΅ΡΡΠ² ΠΎΠΏΡΠ΅Π΄Π΅Π»ΡΠ΅ΡΡΡ Π½Π°ΠΈΠ±ΠΎΠ»Π΅Π΅ ΡΡΡΠ΅ΠΊΡΠΈΠ²Π½ΡΠΉ
ΠΠΎΠ΄ΠΈΡΠΈΠΊΠ°ΡΠΈΡ Π°Π»Π³ΠΎΡΠΈΡΠΌΠ° ΠΊΠ°Π½Π½ΠΈ ΠΏΡΠΈΠΌΠ΅Π½ΠΈΡΠ΅Π»ΡΠ½ΠΎ ΠΊ ΠΎΠ±ΡΠ°Π±ΠΎΡΠΊΠ΅ ΡΠ΅Π½ΡΠ³Π΅Π½ΠΎΠ³ΡΠ°ΡΠΈΡΠ΅ΡΠΊΠΈΡ ΠΈΠ·ΠΎΠ±ΡΠ°ΠΆΠ΅Π½ΠΈΠΉ
Π Π°ΡΡΠΌΠΎΡΡΠ΅Π½Π° ΠΌΠΎΠ΄ΠΈΡΠΈΠΊΠ°ΡΠΈΡ Π°Π»Π³ΠΎΡΠΈΡΠΌΠ° ΠΎΠΏΡΠ΅Π΄Π΅Π»Π΅Π½ΠΈΡ Π³ΡΠ°Π½ΠΈΡ ΠΠ°Π½Π½ΠΈ Π΄Π»Ρ Π±ΡΡΡΡΠΎΠ³ΠΎ Π²ΡΠ΄Π΅Π»Π΅Π½ΠΈΡ ΠΈ ΠΏΠΎΠΈΡΠΊΠ° ΠΏΠΎΠ»ΠΎΠΆΠ΅Π½ΠΈΡ ΠΎΠ±ΡΠ΅ΠΊΡΠ° Π½Π° ΡΠ΅Π½ΡΠ³Π΅Π½ΠΎΠ³ΡΠ°ΡΠΈΡΠ΅ΡΠΊΠΎΠΌ ΠΈΠ·ΠΎΠ±ΡΠ°ΠΆΠ΅Π½ΠΈΠΈ, ΡΡΡΠ°Π½ΠΎΠ²Π»Π΅Π½Π° Π²ΠΎΠ·ΠΌΠΎΠΆΠ½ΠΎΡΡΡ Π°Π²ΡΠΎΠΌΠ°ΡΠΈΠ·ΠΈΡΠΎΠ²Π°Π½Π½ΠΎΠΉ Π½Π°ΡΡΡΠΎΠΉΠΊΠΈ ΠΏΠ°ΡΠ°ΠΌΠ΅ΡΡΠΎΠ² ΠΏΡΠΈ Π½ΠΎΡΠΌΠ°Π»ΠΈΠ·Π°ΡΠΈΠΈ Π³ΠΈΡΡΠΎΠ³ΡΠ°ΠΌΠΌΡ ΠΈΠ·ΠΎΠ±ΡΠ°ΠΆΠ΅Π½ΠΈΡ
Efficient ASIC Architectures for Low Latency Niederreiter Decryption
Post-quantum cryptography addresses the increasing threat that quantum computing poses to modern communication systems. Among the available quantum-resistant systems, the Niederreiter cryptosystem is positioned as a conservative choice with strong security guarantees. As a code-based cryptosystem, the Niederreiter system enables high performance operations and is thus ideally suited for applications such as the acceleration of server workloads. However, until now, no ASIC architecture is available for low latency computation of Niederreiter operations. Therefore, the present work targets the design, implementation and optimization of tailored archi- tectures for low latency Niederreiter decryption. Two architectures utilizing different decoding algorithms are proposed and implemented using a 22nm FDSOI CMOS technology node. One of these optimized architectures improves the decryption latency by 27% compared to a state-of-the-art reference and requires at the same time only 25% of the area
neuroAIx-Framework: design of future neuroscience simulation systems exhibiting execution of the cortical microcircuit model 20Γ faster than biological real-time
IntroductionResearch in the field of computational neuroscience relies on highly capable simulation platforms. With real-time capabilities surpassed for established models like the cortical microcircuit, it is time to conceive next-generation systems: neuroscience simulators providing significant acceleration, even for larger networks with natural density, biologically plausible multi-compartment models and the modeling of long-term and structural plasticity.MethodsStressing the need for agility to adapt to new concepts or findings in the domain of neuroscience, we have developed the neuroAIx-Framework consisting of an empirical modeling tool, a virtual prototype, and a cluster of FPGA boards. This framework is designed to support and accelerate the continuous development of such platforms driven by new insights in neuroscience.ResultsBased on design space explorations using this framework, we devised and realized an FPGA cluster consisting of 35 NetFPGA SUME boards.DiscussionThis system functions as an evaluation platform for our framework. At the same time, it resulted in a fully deterministic neuroscience simulation system surpassing the state of the art in both performance and energy efficiency. It is capable of simulating the microcircuit with 20Γ acceleration compared to biological real-time and achieves an energy efficiency of 48nJ per synaptic event
Efficient ASIC Architecture for Low Latency Classic McEliece Decoding
Post-quantum cryptography addresses the increasing threat that quantum computing poses to modern communication systems. Among the available βquantum-resistantβ systems, the Classic McEliece key encapsulation mechanism (KEM) is positioned as a conservative choice with strong security guarantees. Building upon the code-based Niederreiter cryptosystem, this KEM enables high performance encapsulation and decapsulation and is thus ideally suited for applications such as the acceleration of server workloads. However, until now, no ASIC architecture is available for low latency computation of Classic McEliece operations. Therefore, the present work targets the design, implementation and optimization of a tailored ASIC architecture for low latency Classic McEliece decoding. An efficient ASIC design is proposed, which was implemented and manufactured in a 22 nm FDSOI CMOS technology node. We also introduce a novel inversionless architecture for the computation of error-locator polynomials as well as a systolic array for combined syndrome computation and polynomial evaluation. With these approaches, the associated optimized architecture improves the latency of computing error-locator polynomials by 47% and the overall decoding latency by 27% compared to a state-of-the-art reference, while requiring only 25% of the area
Classification of Resilience Techniques Against Functional Errors at Higher Abstraction Layers of Digital Systems
Nanoscale technology nodes bring reliability concerns back to the center stage of digital system design. A systematic classification of approaches that increase system resilience in the presence of functional hardware (HW)-induced errors is presented, dealing with higher system abstractions, such as the (micro) architecture, the mapping, and platform software (SW). The field is surveyed in a systematic way based on nonoverlapping categories, which add insight into the ongoing work by exposing similarities and differences. HW and SW solutions are discussed in a similar fashion so that interrelationships become apparent. The presented categories are illustrated by representative literature examples to illustrate their properties. Moreover, it is demonstrated how hybrid schemes can be decomposed into their primitive components
Resolving the Memory Bottleneck for Single Supply Near-Threshold Computing
This paper focuses on a review of state-of-the-art memory designs and new design methods for near-threshold computing (NTC). In particular, it presents new ways to design reliable low-voltage NTC memories cost-effectively by reusing available cell libraries, or by adding a digital wrapper around existing commercially available memories. The approach is based on modeling at system level supported by silicon measurement on a test chip in a 40nm low-power processing technology. Advanced monitoring, control and run-time error mitigation schemes enable the operation of these memories at the same optimal near-Vt voltage level as the digital logic. Reliability degradation is thus overcome and this opens the way to solve the memory bottleneck in NTC systems. Starting from the available 40 nm silicon measurements, the analysis is extended to future 14 and 10 nm technology nodes
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