15 research outputs found

    A minimum-energy-based capacitor voltage balancing control strategy for MPC conversion systems

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    In AC/DC/AC power conversion, the connection of a multi point clamped (MPC) rectifier with an MPC inverter simplifies the balancing of the voltages on the series-connected DC link capacitors as well as giving input power-factor correction capability. This is only true provided that an alternative balancing PWM control strategy is adopted instead of the standard PWM one. A control strategy is proposed which is based on the development of an energy function which may be minimized in real time by exploiting the existing redundancies in power-converter switching states. This strategy may be easily implemented in a DSP controller and is usable with any number of voltage levels and input/output phases. A validation has been performed by simulating a 5-level 3-phase MPC system and the significant waveforms are presente

    Mechanisms through which Sos-1 coordinates the activation of Ras and Rac

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    Signaling from receptor tyrosine kinases (RTKs)* requires the sequential activation of the small GTPases Ras and Rac. Son of sevenless (Sos-1), a bifunctional guanine nucleotide exchange factor (GEF), activates Ras in vivo and displays Rac-GEF activity in vitro, when engaged in a tricomplex with Eps8 and E3b1–Abi-1, a RTK substrate and an adaptor protein, respectively. A mechanistic understanding of how Sos-1 coordinates Ras and Rac activity is, however, still missing. Here, we demonstrate that (a) Sos-1, E3b1, and Eps8 assemble into a tricomplex in vivo under physiological conditions; (b) Grb2 and E3b1 bind through their SH3 domains to the same binding site on Sos-1, thus determining the formation of either a Sos-1–Grb2 (S/G) or a Sos-1–E3b1–Eps8 (S/E/E8) complex, endowed with Ras- and Rac-specific GEF activities, respectively; (c) the Sos-1–Grb2 complex is disrupted upon RTKs activation, whereas the S/E/E8 complex is not; and (d) in keeping with the previous result, the activation of Ras by growth factors is short-lived, whereas the activation of Rac is sustained. Thus, the involvement of Sos-1 at two distinct and differentially regulated steps of the signaling cascade allows for coordinated activation of Ras and Rac and different duration of their signaling within the cell

    Analytical models and optimal control of multilevel multi point clamped converters

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    Dottorato di ricerca in ingegneria elettrica. 12. ciclo. Coordinatore Sandro Bertini. Docente di riferimento Maurizio MazzucchelliConsiglio Nazionale delle Ricerche - Biblioteca Centrale - P.le Aldo Moro, 7, Rome; Biblioteca Nazionale Centrale - Piazza Cavalleggeri, 1, Florence / CNR - Consiglio Nazionale delle RichercheSIGLEITItal

    Carrier-less fault-tolerant stochastic synthesis in multi-cell multi-level converters : a central limit approach to highly-dimensional power electronic systems

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    As the number of cells in multi-level converters increase, issues related to the high number of subsystems enter the power electronics area. Within this frame, this study presents a carrier-less approach to the voltage synthesis across the series of several voltage-source cells in multi-level converter topologies. The key idea is the exploitation of a stochastic-based choice of the discrete cell output voltage, operating according to a local, independent random variable. When the number of cells is sufficiently high, the law of large numbers and the central limit theorem (CLT) of the probability theory guarantee that the synthesis of the total voltage lies in a known interval with high probability. Because of the CLT stochastic properties, an increased number of cells inherently leads to more robust and faulttolerant waveforms, also due to the reduced capacitors required in each cell. The absence of deterministic modulation reduces the hardware cost (cabling and control) and requires no reconfiguration in case of cell failures. This work focuses on the theoretical and hardware-in-the-loop validation of the main principle, including an analysis of the capacitance requirements for each cell. The method could be also applied to current-source multi-level converters based on parallel connections of current-source cells.QC 20181211</p

    Fault tolerant cost-effective carrierless stochastic synthesis of voltages and currents in multi-Cell multilevel converters via the central limit theorem

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    The paper presents with experimental evidence a highly fault tolerant, cost-effective and carrierless solution to synthesize voltages (or currents) across the series (or parallel) connection of several voltage-source (or current-source) cells. Hundreds of voltage-source cells already characterize modern multilevel HVDC converters and structures based on current-source cells could become industrially meaningful too, if sufficient advancements in semiconductor and magnetic materials will occur. Exactly by relying on a large number of cells, the key approach is characterized by an unconventional absence of any determinism. The voltages (or currents) of all cells are generated as discrete independent random variables whose distribution is parameterized by the desired reference waveform to be synthesized. This is a radical difference from the already existing random PWM modulations, where only the switching instants are aleatory. The essence of the proposed method lies in observing that multilevel converters, which synthesize the desired waveforms through additive linear combinations (e.g. the simplest sum) of several elementary contributions, become naturally ruled by the Central Limit Theorem of the theory of probablity. Such a fundamental law of nature assures also that the greater the number of cells, the more the waveform synthesis becomes inherently robust, fault-tolerant and accurate. This property strikingly differs from those of deterministic centrally ruled modulations and it is also achieved with reduced hardware complexity and cost. The proposed method benefits from emerging technologies employing smaller mass-produced cells based on devices capable of improved switching characteristics, like SiC or GaN, thereby suiting design philosophies characterized by a high number of cost-optimized standard elementary units. Equally important, the proposed synthesis eliminates most physical communication channels (e.g. optical fibers) among the controller and the switches, thereby greatly improving the system reliability. The paper introduces also a hybrid variant of the method conceived for fewer cells.QC 20181211</p
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