Space Shuttle: A test vehicle for the reliability of the SkyWater 130nm PDK for future space processors

Recently the ASIC industry experiences a massive change with more and more small and medium businesses entering the custom ASIC development. This trend is fueled by the recent open hardware movement and relevant government and privately funded initiatives. These new developments can open new opportunities in the space sector – which is traditionally characterised by very low volumes and very high non-recurrent (NRE) costs – if we can show that the produced chips have favourable radiation properties. In this paper, we describe the design and tape-out of Space Shuttle, the first test chip for the evaluation of the suitability of the SkyWater 130nm PDK and the OpenLane EDA toolchain using the Google/E-fabless shuttle run for future space processors.This work was supported by ESA through the 4000136514/21/NL/GLC/my co-funded PhD activity ”Mixed Software/Hardware-based Fault-tolerance Techniques for Complex COTS System-on-Chip in Radiation Environments”. Moreover, it was partially supported by the Spanish Ministry of Economy and Competitiveness under grants PID2019-107255GB-C21 and IJC2020-045931-I (Spanish State Research Agency / http://dx.doi.org/10.13039/501100011033) and the European Community’s Horizon Europe programme under the METASAT project (grant agreement 101082622).Peer ReviewedPostprint (author's final draft

Space compression algorithms acceleration on embedded multi-core and GPU platforms

Future space missions will require increased on-board computing power to process and compress massive amounts of data. Consequently, embedded multi-core and GPU platforms are considered, which have been shown beneficial for data processing. However, the acceleration of data compression - an inherently sequential task - has not been explored. In this on-going research paper, we parallelize two space compression standards on both CPUs and GPUs using two candidate embedded GPU platforms for space showing that despite the challenging nature of CCSDS algorithms, their parallelization is possible and can provide significant performance benefits.This work was funded by the Ministerio de Ciencia e Innovacion - Agencia Estatal de Investigacion (PID2019-107255GBC21/AEI/10.13039/501100011033 and IJC-2020-045931-I) and partially supported by the European Space Agency (ESA) through the GPU4S (GPU for Space) activity and the HiPEAC Network of Excellence.Peer ReviewedPostprint (author's final draft

Space shuttle: a test vehicle for the reliability of the SkyWater 130nm PDK using OpenLane and the Google/E-fabless shuttle run for future space systems

The ASIC industry is experiencing a massive change in the recent years with more and more small and medium business entering the custom ASIC development. This trend is fueled by the recent open hardware movement and relevant government and privately funded initiatives. These new developments can open new opportunities in the space sector, which is traditionally characterised by very low volumes and very high non-recurrent (NRE) costs, if we can show that the produced chips have favourable radiation properties. In this ACM SRC entry, we describe the design and tape-out of Space Shuttle, the first test chip for the evaluation of the suitability of the SkyWater 130nm PDK and the OpenLane EDA toolchain using the Google/E-fabless shuttle run for future space processors

Sources of single event effects in the NVIDIA Xavier SoC family under proton irradiation

In this paper we characterise two embedded GPU devices from the NVIDIA Xavier family System-on-Chip (SoC) using a proton beam. We compare the NVIDIA Xavier NX and Industrial devices, that respectively target commercial and automotive applications. We evaluate the Single-Event Effect (SEE) rate of both modules and their sub-components, both the CPU and GPU, using different power modes, and we try for the first time to identify their exact sources using the on-line testing facilities included in their ARM based system. Our conclusion is that the most sensitive part of the CPU complex of the SoC is the tag array of the various cache structures, while no errors were observed in the GPU, probably because of its fast execution compared to the CPU part of the application during the radiation campaign.This work was supported by ESA through the 4000136514/21/NL/GLC/my co-funded PhD activity ”Mixed Software/Hardware-based Fault-tolerance Techniques for Complex COTS System-on-Chip in Radiation Environments” and the GPU4S (GPU for Space) project. Moreover, it was partially supported by the Spanish Ministry of Economy and Competitiveness under grants PID2019-107255GB-C21 and IJC2020-045931-I (Spanish State Research Agency / http://dx.doi.org/10.13039/501100011033) and the HiPEAC Network of Excellence.Peer ReviewedPostprint (author's final draft

Functional and timing implications of transient faults in critical systems

Embedded systems in critical domains, such as auto-motive, aviation, space domains, are often required to guarantee both functional and temporal correctness. Considering transient faults, fault analysis and mitigation approaches are implemented at various levels of the system design, in order to maintain the functional correctness. However, transient faults and their mitigation methods have a timing impact, which can affect the temporal correctness of the system. In this work, we expose the functional and the timing implications of transient faults for critical systems. More precisely, we initially highlight the timing effect of transient faults occurring in the combinational and sequential logic of a processor. Furthermore, we propose a full stack vulnerability analysis that drives the design of selective hardware-based mitigation for real-time applications. Last, we study the timing impact of software-based reliability mitigation methods applied in a COTS GPU, using a fault tolerant middleware.This work has been partially funded by ANR-FASY (ANR-21-CE25-0008-01) and received funding by ESA through the 4000136514/21/NL/GLC/my co-funded PhD activity ”Mixed Software/Hardware-based Fault-tolerance Techniques for Complex COTS System-on-Chip in Radiation Environments” and the GPU4S (GPU for Space) project. Moreover, it was partially supported by the Spanish Ministry of Economy and Competitiveness under grants PID2019-107255GB-C21 and IJC2020-045931-I (Spanish State Research Agency / http://dx.doi.org/10.13039/501100011033), by the European Union’s Horizon 2020 grant agreement No 739551 (KIOS CoE) and from the Government of the Republic of Cyprus through the Cyprus Deputy Ministry of Research, Innovation and Digital Policy.Peer ReviewedPostprint (author's final draft

Evaluation of the multicore performance capabilities of the next generation flight computers

Multicore architectures are currently under adoption in the aerospace domain, however their software remains single-threaded. In this paper we argue about the benefits offered by homogeneous parallel processing, both in terms of performance, which is necessary for the implementation of advanced functionalities, as well as in terms of certification and in particular about mastering multicore interference.We discuss the implementation details of this programming paradigm in avionics and space real-time operating systems. We experimentally evaluate the performance benefits offered by several high-performance multicore platforms which are considered good candidates for next generation flight computers, using homogeneous parallel processing under a qualifiable real-time operating system used in the aerospace domain. Our results indicate near to linear speed-ups compared to traditional sequential processing, showing the benefits of this approach.This work was supported by the European Union’s Horizon Europe programme under the METASAT project (grant agreement 101082622). In addition, it was supported by ESA through the 4000136514/21/NL/GLC/my co-funded PhD activity ”Mixed Software/Hardware-based Fault-tolerance Techniques for Complex COTS System-on-Chip in Radiation Environments” and the GPU4S (GPU for Space) ESAfunded project. It was also partially supported by the Spanish Ministry of Economy and Competitiveness under grants PID2019-107255GB-C21 and IJC-2020-045931-I ( Spanish State Research Agency / Agencia Española de Investigación (AEI) / http://dx.doi.org/10.13039/501100011033 ) and by the Department of Research and Universities of the Government of Catalonia with a grant to the CAOS Research Group (Code: 2021 SGR 00637).Peer ReviewedPostprint (author's final draft

Real-Time Simulations of SpaceWire On-board Data Handling Networks

SpaceWire is a widely used on-board data-handling network technology for spacecraft.This project aimed to investigate the way in which SpaceWire is being used in on-board data handling networks on scientific spacecraft.A real-time SpaceWire network simulation was made, modeled on the data handling networks of the future ESA missions BepiColombo MPO and Solar Orbiter.The CCSDS space packet protocol and the ECSS Packet Utilization Standard (PUS) were employed for the structuring of packets in the simulation.The SpaceWire EGSE device from STAR-Dundee Ltd. was used to perform simulations of scientific instruments using SpaceWire. Multiple scripts for the EGSE device were created to simulate the packet generation behavior of the different configuration of the instruments.Software for control and monitoring of multiple EGSE was implemented. A prototype for a generic PUS network node software was also developed. Additionally packet libraries for CCSDS and PUS were developed.A demonstration network was built using SpaceWire testing equipment, encompassingall of the developed tools.Finally the EGSE was evaluated in conjunction with the simulation, including the device’s support for generating CCSDS and PUS packets. Several improvements and additional features for the EGSE device and scripting language were suggested.Validerat; 20141204 (global_studentproject_submitter