Micro-Fabrication of Planar Inductors for High Frequency DC-DC Power Converters

International audienc

Modeling, Fabrication, and Characterization of Planar Inductors on YIG Substrates

International audienceThis paper presents the design, fabrication, and characterization of micro planar inductors on a microwave magnetic material (YIG). Planar spiral inductors were designed for monolithic DC-DC converters in System-In-Package with 100 MHz switching frequency (1 W, Vin= 3.6 V, Vout= 1 V). A microwave magnetic substrate (YIG) serves as mechanical support, and also presents a double purpose by increasing inductance value and reducing electromagnetic interferences (EMI). This last point is critical to improve the behavior of a switching mode power supply (SMPS). In order to obtain an optimal design for the inductor, geometrical parameters were studied using Flux2D simulator and an optimized 30 to 40 nH spiral inductor with expected 25 mΩ RDC, 3 mm2 footprint area was designed. Subsequently, samples have been fabricated by electroplating technique, and tested using a vector network analyzer in the 10 MHz to 100 MHz frequency range. Results were then compared to the predicted response of simulated equivalent model

Croissance hétéroépitaxiale du SiC-3C sur substrats SiC hexagonaux; Analyses par faisceaux d'ions accélérés des impuretés incorporées

Using silicon as substrate for growing 3C-SiC monocrystalline material generates too many defects in the layers due to lattice and thermal expansion mismatch. Though these difficulties are avoided byusing hexagonal SiC substrates, the random formation of 60° rotated domains in the 3C layers generate a high density of twins.The use of vapour phase epitaxy for the growth did not allow reducing significantly the twin densitydespite the optimization of the in situ surface preparation of the seeds. On the other hand, these defects were eliminated by using Vapor-Liquid-Solid mechanism which consists in feeding a Si-Ge melt withpropane.The characterization of these twin-free layers showed excellent crystalline quality. Some of theimpurities incorporated during growth (Ge, Al, B, Sn) were successfully analysed using acceleratedion beam techniques though the detection and quantification of these elements inside SiC thin filmsare challenging.L'utilisation de germes Si pour l'épitaxie du SiC-3C génère de nombreux défauts dans les couches enraison du désaccord de maille et de la dilatation thermique. Le SiC-3C peut aussi être déposé sursubstrats SiC-α(0001) en s'affranchissant des problèmes rencontré sur substrat Si. La difficulté decontrôler la germination initiale génère cependant des macles qui sont difficiles à éviter ou éliminerensuite.L'utilisation de l'épitaxie en phase vapeur comme technique de croissance n'a pas permis des'affranchir de ces macles malgré l'optimisation de la préparation de surface des germes SiC- α. En revanche, des couches de SiC-3C exemptes de macle ont été obtenues en utilisant une technique decroissance originale, les mécanismes vapeur-liquid-solide, qui consiste à alimenter un bain Si-Ge avecdu propane.La caractérisation des couches ainsi élaborées a montré une excellente qualité cristalline avec toutefois une incorporation non négligeable d'impuretés. Les éléments Al, Ge, B et Sn ont été dosés avec succès en utilisant des analyses par faisceaux d'ions accélérés, techniques peu conventionnelles pour SiC et présentant un challenge analytique

Croissance hétéroépitaxiale du SiC-3C sur substats SiC hexagonaux (analyses par faisceaux d'ions accélérés des impuretés incorporées)

L utilisation de germes Si pour l épitaxie du SiC-3C génère de nombreux défauts dans les couches en raison du désaccord de maille et de la dilatation thermique. Le SiC-3C peut aussi être déposé sur substrats SiC-a(0001) en s affranchissant des problèmes rencontré sur substrat Si. La difficulté de contrôler la germination initiale génère cependant des macles qui sont difficiles à éviter ou éliminer ensuite. L'utilisation de l'épitaxie en phase vapeur comme technique de croissance n'a pas permis de s'affranchir de ces macles malgré l'optimisation de la préparation de surface des germes SiC- a. En revanche, des couches de SiC-3C exemptes de macle ont été obtenues en utilisant une technique de croissance originale, les mécanismes vapeur-liquid-solide, qui consiste à alimenter un bain Si-Ge avec du propane. La caractérisation des couches ainsi élaborées a montré une excellente qualité cristalline avec toutefois une incorporation non négligeable d'impuretés. Les éléments Al, Ge, B et Sn ont été dosés avec succès en utilisant des analyses par faisceaux d ions accélérés, techniques peu conventionnelles pour SiC et présentant un challenge analytique.Using silicon as substrate for growing 3C-SiC monocrystalline material generates too many defects in the layers due to lattice and thermal expansion mismatch. Though these difficulties are avoided by using hexagonal SiC substrates, the random formation of 60 rotated domains in the 3C layers generate a high density of twins. The use of vapour phase epitaxy for the growth did not allow reducing significantly the twin density despite the optimization of the in situ surface preparation of the seeds. On the other hand, these defects were eliminated by using Vapor-Liquid-Solid mechanism which consists in feeding a Si-Ge melt with propane. The characterization of these twin-free layers showed excellent crystalline quality. Some of the impurities incorporated during growth (Ge, Al, B, Sn) were successfully analysed using accelerated ion beam techniques though the detection and quantification of these elements inside SiC thin films are challengingLYON1-BU.Sciences (692662101) / SudocSudocFranceF

Full densification of molybdenum powders and multilayer materials obtained by Spark Plasma Sintering

International audienceMolybdenum powders with two different particle sizes were sintered using the Spark Plasma Sintering (SPS) process. A near to 1 density are obtained in a few minutes. A Molybdenum/Aluminum Nitride multilayer was obtained while sintering in one step, using the SPS process

Growth of Nanocrystalline Translucent h-BN Films Deposited by CVD at High Temperature on SiC Substrates

International audienc

A Lab-Scale Alternative Interconnection Solution of Semiconductor Dice Compatible with Power Modules 3-D Integration

International audienceIncrease in the power density of power modules requires an interconnection technology alternative to wire bonding technology. Emerging interconnection technologies allow a three-dimensional packaging of power modules. A proposal of interconnection solution for the power semiconductor dice is presented here : it is based on copper micro-posts that are electroplated on top side of the die. The die with its micro-posts is then attached to a top Direct Bonding Copper substrate using a copper/tin transient liquid phase technique. The assembly of the backside of the die to a bottom Direct Bonding Copper substrate is processed concurrently using the same transient liquid phase technique. The benefits or limitations of the substrate on the assembly are not discussed in this paper. Manufacturing and electrical characterization of a power semiconductor die with the micro-posts interconnection is presented in detail

Mechanical Study of Copper Bonded at Low Temperature Using Spark Plasma Sintering Process

International audienceIn this study, bonding of high purity polished copper was investigated using the Spark Plasma Sintering technique (SPS) showing the effect of SPS parameters on the bonding strength and on the microstructural behaviour

Deposition of nanocrystalline translucent h-BN films by chemical vapor deposition at high temperature

International audienc

Process Optimization for High Temperature SiC Lateral Devices

International audienceComplementary lateral structures, N-JFETs. P-JFETS and bipolar diodes, have been implemented in p and n-type 4H-SiC wafers with epilayers. The device were optimized using finite element code MEDICI (TM) simulations, based oil ion implanted and etched Reduced-Surface-Field structures. Two Ti/Ni alloy composition are found to form ohmic contacts compatibles with high temperature device operation. 900 degrees C and respectively 1000 degrees C post-metallisation annealing during 2min are necessary. The presence of a graphite layer is determined by XPS (X-ray photon spectroscopy) analyses at the metal-semiconductor interface. Oil the fabricated p and n-type lateral JFETs in blocking state, breakdown voltage as high as 600V are obtained