Analysis of the Implications of Stacked Devices in Nano-Scale Technologies for Analog Applications

In this work, a methodology to assess the implications on the performance of analog circuits due to the use of stacked devices in current nano-scale technologies is presented. To evaluate the usage of stacked devices, the characteristic curves of transistors implemented with a different amount of transistors in stack are obtained and compared to those of a single device. The effects of using stacked devices are further studied with the implementation of a current mirror and the implementation of two different layout topologies, discussing their tradeoffs, advantages and drawbacks. Our methodology facilitates designers to develop a good understanding of the characteristics and limitations of a particular physical design before silicon is back for laboratory testing

A Tool for the Automatic Generation and Analysis of Regular Analog Layout Modules

This paper describes the characteristics of a new CAD tool that enables the creation of layout libraries of selected analog modules. This Analog Modules Generator (AMG) automatically creates multiple layout versions of two commonly used analog structures: the differential pair and arrays of series-connected or stacked devices, for the subsequent generation of layout libraries. Based on the number of devices and rows defined by the user for the layout implementation, the tool validates all possible implementations, which are later saved in a database with their corresponding characteristics, such as area and parasitics information. Additionally, an extraction process can be optionally executed over all the layout views saved in the database. The AMG generates several reports with all the characteristics of the implemented layouts, including area and parasitic components, facilitating further statistical processing. We describe the features and capabilities of the proposed AMG tool, and several test cases are presented. Results show that optimal layout implementations can be achieved by layout and circuit designers in a reduced amount of time

Synthesis tool for automatic layout generation of analog structures

In this paper, a novel analog layout synthesis tool is presented. It is focused on two common analog building blocks: differential pairs and arrays of stacked devices. Starting from a circuit netlist and the names of the selected transistors, the tool verifies that these form a valid block and creates the corresponding layout. The user can define different layout parameters and the layout view can be generated with different levels of detail. Multiple layout views of a differential pair are generated to show its effectiveness to speed up the design process