45 research outputs found
Expression of bone morphogenetic protein 2 and fibroblast growth factor 2 during bone regeneration using different implant meterials as an onlay bone graft in rabbit mandibles
取得学位 : 博士(医学), 学位授与番号 : 医博甲第1806号, 学位授与年月日 : 平成18年9月28日, 学位授与大学 : 金沢大学, 主査教授 : 山本 悦秀, 副査教授 : 富田 勝郎, 古川
Cryogenic Memory Technologies
The surging interest in quantum computing, space electronics, and
superconducting circuits has led to new developments in cryogenic data storage
technology. Quantum computers promise to far extend our processing capabilities
and may allow solving currently intractable computational challenges. Even with
the advent of the quantum computing era, ultra-fast and energy-efficient
classical computing systems are still in high demand. One of the classical
platforms that can achieve this dream combination is superconducting single
flux quantum (SFQ) electronics. A major roadblock towards implementing scalable
quantum computers and practical SFQ circuits is the lack of suitable and
compatible cryogenic memory that can operate at 4 Kelvin (or lower)
temperature. Cryogenic memory is also critically important in space-based
applications. A multitude of device technologies have already been explored to
find suitable candidates for cryogenic data storage. Here, we review the
existing and emerging variants of cryogenic memory technologies. To ensure an
organized discussion, we categorize the family of cryogenic memory platforms
into three types: superconducting, non-superconducting, and hybrid. We
scrutinize the challenges associated with these technologies and discuss their
future prospects.Comment: 21 pages, 6 figures, 1 tabl
Compact Model of a Topological Transistor
The precession of a ferromagnet leads to the injection of spin current and
heat into an adjacent non-magnetic material. Besides, spin-orbit entanglement
causes an additional charge current injection. Such a device has been recently
proposed where a quantum-spin hall insulator (QSHI) in proximity to a
ferromagnetic insulator (FI) and superconductor (SC) leads to the pumping of
charge, spin, and heat. Here we build a circuit-compatible Verilog-A-based
compact model for the QSHI-FI-SC device capable of generating two topologically
robust modes enabling the device operation. Our model also captures the
dependence on the ferromagnetic precision, drain voltage, and temperature with
an excellent (> 99%) accuracy
CMOS-based Single-Cycle In-Memory XOR/XNOR
Big data applications are on the rise, and so is the number of data centers.
The ever-increasing massive data pool needs to be periodically backed up in a
secure environment. Moreover, a massive amount of securely backed-up data is
required for training binary convolutional neural networks for image
classification. XOR and XNOR operations are essential for large-scale data copy
verification, encryption, and classification algorithms. The disproportionate
speed of existing compute and memory units makes the von Neumann architecture
inefficient to perform these Boolean operations. Compute-in-memory (CiM) has
proved to be an optimum approach for such bulk computations. The existing
CiM-based XOR/XNOR techniques either require multiple cycles for computing or
add to the complexity of the fabrication process. Here, we propose a CMOS-based
hardware topology for single-cycle in-memory XOR/XNOR operations. Our design
provides at least 2 times improvement in the latency compared with other
existing CMOS-compatible solutions. We verify the proposed system through
circuit/system-level simulations and evaluate its robustness using a 5000-point
Monte Carlo variation analysis. This all-CMOS design paves the way for
practical implementation of CiM XOR/XNOR at scaled technology nodes.Comment: 12 pages, 6 figures, 1 tabl
Cryogenic Neuromorphic Hardware
The revolution in artificial intelligence (AI) brings up an enormous storage
and data processing requirement. Large power consumption and hardware overhead
have become the main challenges for building next-generation AI hardware. To
mitigate this, Neuromorphic computing has drawn immense attention due to its
excellent capability for data processing with very low power consumption. While
relentless research has been underway for years to minimize the power
consumption in neuromorphic hardware, we are still a long way off from reaching
the energy efficiency of the human brain. Furthermore, design complexity and
process variation hinder the large-scale implementation of current neuromorphic
platforms. Recently, the concept of implementing neuromorphic computing systems
in cryogenic temperature has garnered intense interest thanks to their
excellent speed and power metric. Several cryogenic devices can be engineered
to work as neuromorphic primitives with ultra-low demand for power. Here we
comprehensively review the cryogenic neuromorphic hardware. We classify the
existing cryogenic neuromorphic hardware into several hierarchical categories
and sketch a comparative analysis based on key performance metrics. Our
analysis concisely describes the operation of the associated circuit topology
and outlines the advantages and challenges encountered by the state-of-the-art
technology platforms. Finally, we provide insights to circumvent these
challenges for the future progression of research
A Review on Digital Pixel Sensors
Digital pixel sensor (DPS) has evolved as a pivotal component in modern
imaging systems and has the potential to revolutionize various fields such as
medical imaging, astronomy, surveillance, IoT devices, etc. Compared to analog
pixel sensors, the DPS offers high speed and good image quality. However, the
introduced intrinsic complexity within each pixel, primarily attributed to the
accommodation of the ADC circuit, engenders a substantial increase in the pixel
pitch. Unfortunately, such a pronounced escalation in pixel pitch drastically
undermines the feasibility of achieving high-density integration, which is an
obstacle that significantly narrows down the field of potential applications.
Nonetheless, designing compact conversion circuits along with strategic
integration of 3D architectural paradigms can be a potential remedy to the
prevailing situation. This review article presents a comprehensive overview of
the vast area of DPS technology. The operating principles, advantages, and
challenges of different types of DPS circuits have been analyzed. We categorize
the schemes into several categories based on ADC operation. A comparative study
based on different performance metrics has also been showcased for a
well-rounded understanding
Superconducting Heater Cryotron-Based Reconfigurable Logic Towards Cryogenic IC Camouflaging
Superconducting electronics are among the most promising alternatives to
conventional CMOS technology thanks to the ultra-fast speed and ultra-high
energy efficiency of the superconducting devices. Having a cryogenic control
processor is also a crucial requirement for scaling the existing quantum
computers up to thousands of qubits. Despite showing outstanding speed and
energy efficiency, Josephson junction-based circuits suffer from several
challenges such as flux trapping leading to limited scalability, difficulty in
driving high impedances, and so on. Three-terminal cryotron devices have been
proposed to solve these issues which can drive high impedances (>100 k{\Omega})
and are free from any flux trapping issue. In this work, we develop a
reconfigurable logic circuit using a heater cryotron (hTron). In conventional
approaches, the number of devices to perform a logic operation typically
increases with the number of inputs. However, here, we demonstrate a single
hTron device-based logic circuit that can be reconfigured to perform 1-input
copy and NOT, 2-input AND and OR, and 3-input majority logic operations by
choosing suitable biasing conditions. Consequently, we can perform any
processing task with a much smaller number of devices. Also, since we can
perform different logic operations with the same circuit (same layout), we can
develop a camouflaged system where all the logic gates will have the same
layout. Therefore, this proposed circuit will ensure enhanced hardware security
against reverse engineering attacks.Comment: 12 pages, 5 figure
Effect of age on immediate postoperative tissue reaction following surgical extraction of impacted mandibular third molar
Background: Postoperative morbidity following third molar surgery is affected by a number of factors. The aim of this study was to determine the effect of age on immediate postoperative tissue reactions following mandibular impacted third molar surgery. Objectives: To assess the discomforts after impacted mandibular third molar extraction in different aged patient. Methods: 100 patients, 54 Female and 46 male, aged 18 to 42 years comprised the study materials. Tooth extraction was performed with buccal guttering technique after adequate elevation and reflection of full thickness mucoperiosteal flap. Pain, swelling and trismus were evaluated preoperatively and on 2nd POD and 7th POD. Data was processed and analyzed using SPSS and was compiled and test of significance was done using Chi square (x2) test and un-paired 't' test. Results: Statistical analysis of the data indicated that pain and swelling was significantly less and significant maximum mouth opening was achieved in early aged patient than late age when preoperative and postoperative results were compared. Conclusion: As postoperative immediate tissue reactions are more in late aged patient than younger so impacted mandibular third molar should extract in early age
Outcome of surgically resected mandibular ameloblastoma
Ameloblastoma is a slowly growing locally invasive benign tumor of the jaw. Only account for 1% of all tumors of maxillofacial region and 11% of all odontogenic tumors. The Aim of the study was to establis