Power and Area Efficient Design of Network-on-Chip Router through Utilization

Abstract Network-on-Chip (NoC) is the interconnection platform that answers the requirements of the modern on-Chip design. Small optimizations in NoC router architecture can show a significant improvement in the overall performance of NoC based systems. Power consumption, area overhead and the entire NoC performance is influenced by the router buffers. Resource sharing for on-chip network is critical to reduce the chip area and power consumption. Virtual channel buffer sharing by other router ports has been proposed to enhance the performance of on-chip communication. We approach the router architecture optimization by utilizing the idle buffers instead of increasing the number and size of buffers for desired throughput

Synchronization Can Improve Reactive Systems Control and Modularity

We concentrate on two major aspects of reactive system design: behavior control and modularity. These are studied from a formal point of view, within the framework of action systems. The traditional interleaving paradigm is completed with a barrier synchronization mechanism. This is achieved by introducing a new parallel composition operator, applicable to bot h discrete and hybrid models. While offering improvements with respect to control and modularity, the approach uses the correctness preserving mechanisms provided by the underlying reasoning environment 1. 1) A shorter version of this study appeared as "Modular Design of Reactive Systems", in Proceedings of the 28th Annual International Computer Software and Applications Conference (COMPSAC 2004), IEEE Computer Society Press, September 2004, Hong Kong. Pages 265-271