Response of Wheat Crop to Phosphorus Levels and Application Methods

A field study was carried out at New Developmental Farm of Khyber Pakhtunkhwa Agricultural University Peshawar, Pakistan during winter 2010-2011 to investigate the effect of phosphorus levels and application methods on yield and yield components of wheat. The experiment consisted of phosphorus levels (0, 50, 75, 100 and 125 kg ha-1) and application methods (broadcast, single band and double band). Randomized complete block (RCB) design with split plot arrangements having four replications was used. Results indicated that application of phosphorus at the rate of 100 kg ha-1 through double band placement significantly (P<0.05) enhanced plant height, productive tillers m-2, grains spike-1, 1000 grain weight, biological yield, grain yield, harvest index and agronomic phosphorus efficiency of wheat crop and reduced non productive tillers m‑2 compared with other treatments

Cost-Effective TSV Grouping for Yield Improvement of 3D-ICs

Three-dimensional Integrated Circuits (3D-ICs) vertically stack multiple silicon dies to reduce overall wire length, power consumption, and allow integration of heterogeneous technologies. Through-silicon-vias (TSVs) which act as vertical links between layers pose challenges for 3D integration design. TSV defects can happen in fabrication process and bonding stage, which can reduce the yield and increase the cost. Recent work proposed the employment of redundant TSVs to improve the yield of 3D-ICs. This paper presents a redundant TSVs grouping technique, which partition regular and redundant TSVs into groups. For each group, a set of multiplexers are used to select good signal paths away from defective TSVs. We investigate the impact of grouping ratio (regular-to-redundant TSVs in one group) on trade-off between yield and hardware overhead. We also show probabilistic models for yield analysis under the influence of independent and clustering defect distributions. Simulation results show that for a given number of TSVs and TSV failure rate, careful selection of grouping ratios lead to achieving 100% yield at minimal hardware cost (number of multiplexers and redundant TSVs) in comparison to a design that does not exploit TSV grouping ratios

Modeling the Impact of Process Variation on Resistive Bridge Defects

Recent research has shown that tests generated without taking process variation into account may lead to loss of test quality. At present there is no efficient device-level modeling technique that models the effect of process variation on resistive bridges. This paper presents a fast and accurate technique to model the effect of process variation on resistive bridge defects. The proposed model is implemented in two stages: firstly, it employs an accurate transistor model (BSIM4) to calculate the critical resistance of a bridge; secondly, the effect of process variation is incorporated in this model by using three transistor parameters: gate length (L), threshold voltage (V) and effective mobility (ueff) where each follow Gaussian distribution. Experiments are conducted on a 65-nm gate library (for illustration purposes), and results show that on average the proposed modeling technique is more than 7 times faster and in the worst case, error in bridge critical resistance is 0.8% when compared with HSPICE

High quality testing of grid style power gating

This paper shows that existing delay-based testing techniques for power gating exhibit fault coverage loss due to unconsidered delays introduced by the structure of the virtual voltage power-distribution-network (VPDN). To restore this loss, which could reach up to 70.3% on stuck-open faults, we propose a design-for-testability (DFT) logic that considers the impact of VPDN on fault coverage in order to constitute the proper interface between the VPDN and the DFT. The proposed logic can be easily implemented on-top of existing DFT solutions and its overhead is optimized by an algorithm that offers trade-off flexibility between test-application-time and hardware overhead. Through physical layout SPICE simulations, we show complete fault coverage recovery on stuck-open faults and 43.2% test-application-time improvement compared to a previously proposed DFT technique. To the best of our knowledge, this paper presents the first analysis of the VPDN impact on test qualit

The skin barrier: Tape stripping studies

The skin, being an exposed organ, is an easy site to access for research. However, standard interventions, such as a biopsy, leave the skin scarred and are logistically cumbersome. Therefore, non-invasive methods are preferable providing reliable in vivo data can be obtained. The study of the skin barrier is particularly suited to non-invasive techniques, as the ability of the skin to allow molecules to permeate is a dynamic process best seen in living tissue. A widely utilized method is the application of adhesive tapes to the skin. These tapes, when removed, take with them a small amount of stratum corneum that is adherent: this can be studied further, as can the remaining skin at the stripping site. Typical studies performed in this way include studies of "drugs reservoirs" in the stratum corneum (where lipophilic compounds accumulate), studies of the skin barrier to water and other substances, studies of transdermal drug delivery and studies of wound healing and stratum corneum physiology. There is no standardized method for tape stripping, resulting in confusion over technique and difficulty in interpreting other workers' data. Recently there have been attempts to improve the methodology. One such improvement by this laboratory has been the development of a method to quantify the exact amount of stiatum comeum on each tape. This information is expected to advance the use of the tape stripping model considerably particularly because other variables can now be measured against stratum corneum mass and depth. It is the aim of this thesis to take that work forward. The aim of this thesis is to build on a new model of stratum corneum tape stripping and demonstrate its usefulness as a method of studying the stratum corneum, both physiologically and phannacologically. Each of the studies performed has advanced the existing database of knowledge in this field. Study 1 has demonstrated that a variety of tapes can be successfully and generally equivalently used to study skin water kinetics. It has provided a database of information on tape stripping for future investigators and re-calculated water kinetics using the new quantitative data. In addition, this study has identified that a proportion of the population do not display increased transepidermal water loss despite significant barrier damage. This implies that the sheer mass of stratum corneum alone cannot explain the skin barrier to water, but rather there must be other factors such as the proportion of different types of lipids that must be responsible for this. Study 2 has, for the first time, demonstrated a quantitative method to assess the efficacy of keratolytic drugs. In addition, it has refuted a commonly held premise that acids applied to the skin must be at a pH near their pKa in order to retain their efficacy. In fact, this thesis shows that such practice results in increased skin irritation but no increase in efficacy, compared to less acidic preparations of the same acid. This data will allow those who formulate such drugs to make less irritating preparations. Study 3 has, for the first time, localized the acid mantle in vivo in human skin and also confirmed that this acid mantle is distinct from skin surface acidity. Also, this study has discovered a zone in the stratum corneum where pH is almost stable for 1?m, consistently between subjects, suggesting that common metabolic processes are taking place at this site. This information is of use to those who formulate drugs for transdermal delivery, to the study of skin metabolism and to the study of diseases with altered skin pH, such as atopic dermatitis. (Abstract shortened by ProQuest.)

Delay test for diagnosis of power switches

Power switches are used as part of power-gating technique to reduce leakage power of a design. To the best of our knowledge, this is the first work in open-literature to show a systematic diagnosis method for accurately diagnosingpower switches. The proposed diagnosis method utilizes recently proposed DFT solution for efficient testing of power switches in the presence of PVT variation. It divides power switches into segments such that any faulty power switch is detectable thereby achieving high diagnosis accuracy. The proposed diagnosis method has been validated through SPICE simulation using a number of ISCAS benchmarks synthesized with a 90-nm gate library. Simulation results show that when considering the influence of process variation, the worst case loss of accuracy is less than 4.5%; and the worst case loss of accuracy is less than 12% when considering VT (Voltage and Temperature) variations

NBTI and leakage aware sleep transistor design for reliable and energy efficient power gating

In this paper we show that power gating techniques become more effective during their lifetime, since the aging of sleep transistors (STs) due to negative bias temperature instability (NBTI) drastically reduces leakage power. Based on this property, we propose an NBTI and leakage aware ST design method for reliable and energy efficient power gating. Through SPICE simulations, we show lifetime extension up to 19.9x and average leakage power reduction up to 14.4% compared to standard STs design approach without additional area overhead.Finally, when a maximum 10-year lifetime target is considered, we show that the proposed method allows multiple beneficial options compared to a standard STs design method: either to improve circuit operating frequency up to 9.53% or to reduce ST area overhead up to 18.4

BTI and leakage aware dynamic voltage scaling for reliable low power cache memories

We propose a novel dynamic voltage scaling (DVS)approach for reliable and energy efficient cache memories. First, we demonstrate that, as memories age, leakage power reduction techniques become more effective due to sub-threshold current reduction with aging. Then, we provide an analytical model and a design exploration framework to evaluate trade-offs between leakage power and reliability, and propose a BTI and leakage aware selection of the “drowsy” state retention voltage for DVS of cache memories. We propose three DVS policies, allowing us to achieve different power/reliability trade-offs. Through SPICE simulations, we show that a critical charge and a static noise margin increase up to 150% and 34.7%, respectively, is achieved compared to standard aging unaware drowsy technique, with a limited leakage power increase during the very early lifetime, and with leakage energy saving up to 37% in 10 years of operation. These improvements are attained at zero or negligible area cos