Graph Symmetry Detection and Canonical Labeling: Differences and Synergies

Symmetries of combinatorial objects are known to complicate search algorithms, but such obstacles can often be removed by detecting symmetries early and discarding symmetric subproblems. Canonical labeling of combinatorial objects facilitates easy equivalence checking through quick matching. All existing canonical labeling software also finds symmetries, but the fastest symmetry-finding software does not perform canonical labeling. In this work, we contrast the two problems and dissect typical algorithms to identify their similarities and differences. We then develop a novel approach to canonical labeling where symmetries are found first and then used to speed up the canonical labeling algorithms. Empirical results show that this approach outperforms state-of-the-art canonical labelers.Comment: 15 pages, 10 figures, 1 table, Turing-10

Selection of Voltage Thresholds for Delay Measurement

Since all physical devices have a finite non-zero responsetime, the notion of delay between the input and output logicsignals arises naturally once digital abstraction is done. Thisdelay should be positive and non-zero, since a physical devicetakes a finite amount of time to respond to the input. Defininga strictly positive delay is not a problem in the abstract domainof logic signals, since input and output ’’events‘‘ are preciselydefined. However, when the signal non-idealities are accountedfor, the notion of events is blurred and it is not obvious howto define delay such that it reflects the causal relationshipbetween the input and the output. By necessity, we define thestart and end points of these events by determining the timeinstants when the signals cross some appropriate voltage thresholds.The selection of these voltage thresholds for logic gates aswell as simple interconnect wires, is the subject of this paper.We begin by a discussion of what we mean by signal delay andhow it arises in a logic gate. With this background, startingfrom ideal inputs to ideal inverters and concluding with physicalinputs to physical inverters, we examine the problem of thresholdselection for inverters through a logical sequence of model refinement,using a combination of analytical and experimental techniques.Based on the insight gained through this analysis, we examinethe problem for multi-input (both static and dynamic) gates aswell as point-to-point interconnect wires. We show that thresholdsderived from the gate‘s DC voltage transfer characteristic removesthe anomalies, such as negative delay and large sensitivity toinput waveshape effects, that can arise with the widely used50% and 10%–90% thresholds. Despite its fundamentalnature, however, we note that the problem of threshold selectionhas received scant attention in the literature. To the best ofour knowledge, this is the first detailed study of this problem.Peer Reviewedhttp://deepblue.lib.umich.edu/bitstream/2027.42/44035/1/10470_2004_Article_137059.pd

Modeling the effects of temporal proximity of input transitions on gate propagation delay and transition time

Abstract: While delay modeling of gates with a single switching input has received considerable attention, the case of multiple inputs switching in close temporal proximity is just beginning to be addressed in the literature. The effect of proximity of input transitions can be significant on the delay and output transition time. The few attempts that have addressed this issue are based on a series-parallel transistor collapsing method that reduces the multi-input gate to an inverter. This limits the technique to CMOS technology. Moreover, none of them discuss the appropriate choice of voltage thresholds to measure delay for a multi-input gate. In this paper, we first present a method for the choice of voltage thresholds for a multi-input gate that ensures a positive value of delay under all input conditions. We next introduce a dual-input proximity model for the case when only two inputs of the gate are switching. We then propose a simple approximate algorithm for calculating the delay and output transition time that makes repeated use of the dual-input proximity model without collapsing the gate into an equivalent inverter. Comparison with simulation results shows that our method performs quite well in practice

Pueblo: A modern pseudo-boolean sat solver

In this report we introduce a new SAT solver that integrates logic-based reasoning and integer programming meth-ods to systems of CNF and PB constraints. Its novel features include an efficient PB literal watching strategy that takes advantage of the preponderance of unit-coefficient literals in most PB constraints. Additionally, the solver incorporates several PB learning methods that take advantage of the pruning power of PB constraints while mini-mizing their overhead. Empirical evidence suggests that such judicious injection of IP techniques can be quite effec-tive in practice. CSE-TR-492-04: Pueblo: A Modern Pseudo-Boolean SAT Solver 2