241 research outputs found
A fast and retargetable framework for logic-IP-internal electromigration assessment comprehending advanced waveform effects
A new methodology for system-on-chip-level logic-IP-internal electromigration verification is presented in this paper, which significantly improves accuracy by comprehending the impact of the parasitic RC loading and voltage-dependent pin capacitance in the library model. It additionally provides an on-the-fly retargeting capability for reliability constraints by allowing arbitrary specifications of lifetimes, temperatures, voltages, and failure rates, as well as interoperability of the IPs across foundries. The characterization part of the methodology is expedited through the intelligent IP-response modeling. The ultimate benefit of the proposed approach is demonstrated on a 28-nm design by providing an on-the-fly specification of retargeted reliability constraints. The results show a high correlation with SPICE and were obtained with an order of magnitude reduction in the verification runtime.Peer ReviewedPostprint (author's final draft
A general model for performance optimization of sequential systems
Retiming, c-slow retiming and recycling are different transformations for the performance optimization of sequential circuits. For retiming and c-slow retiming, different models that provide exact solutions have already been proposed. An exact model for recycling was yet unknown. This paper presents a general formulation that covers the combination of the three schemes for performance optimization. It provides an exact model based on integer linear programming that resorts to the structural theory of marked graphs. A set of experiments has been designed to show the benefits in performance obtained by combining retiming and recycling. The results also show the applicability of the method in large circuits.Peer ReviewedPostprint (published version
Performance Driven Global Routing Through Gradual Refinement
We propose a heuristic for VLSI interconnect global routing that can optimize routing congestion, delay and number of bends, which are often competing objectives. Routing flexibilities under timing constraints are obtained and exploited to reduce congestion subject to timing constraints. The wire routes are determined through gradual refinement according to probabilistic estimation on congestions so that the congestion is minimized while the number of bends on wires is limited. The experiments on both random generated circuits and benchmark circuits confirm the effectiveness of this method
ECO-CHIP: Estimation of Carbon Footprint of Chiplet-based Architectures for Sustainable VLSI
Decades of progress in energy-efficient and low-power design have
successfully reduced the operational carbon footprint in the semiconductor
industry. However, this has led to an increase in embodied emissions,
encompassing carbon emissions arising from design, manufacturing, packaging,
and other infrastructural activities. While existing research has developed
tools to analyze embodied carbon at the computer architecture level for
traditional monolithic systems, these tools do not apply to near-mainstream
heterogeneous integration (HI) technologies. HI systems offer significant
potential for sustainable computing by minimizing carbon emissions through two
key strategies: ``reducing" computation by reusing pre-designed chiplet IP
blocks and adopting hierarchical approaches to system design. The reuse of
chiplets across multiple designs, even spanning multiple generations of
integrated circuits (ICs), can substantially reduce embodied carbon emissions
throughout the operational lifespan. This paper introduces a carbon analysis
tool specifically designed to assess the potential of HI systems in
facilitating greener VLSI system design and manufacturing approaches. The tool
takes into account scaling, chiplet and packaging yields, design complexity,
and even carbon overheads associated with advanced packaging techniques
employed in heterogeneous systems. Experimental results demonstrate that HI can
achieve a reduction of embodied carbon emissions up to 70\% compared to
traditional large monolithic systems. These findings suggest that HI can pave
the way for sustainable computing practices, contributing to a more
environmentally conscious semiconductor industry.Comment: Under review at HPCA2
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