High-Temperature Organic Rankine Cycle Utilizing Novel Scroll Expander and Pump

Organic Rankine Cycles (ORC) are widely employed to extracting work from different heat sources to improve the operational efficiency of thermal systems. High-temperature ORCs (\u3e 250 – 300 °C) are still particularly challenging especially when hydrocarbons cannot be used as the working fluids. Generators for Small Electric and Thermal Systems (GENSETs) are one example of systems where ORCs can be used as a bottoming cycle. A 1 kWe ORC has been previously constructed to evaluate the feasibility of designing an ORC with a heat source inlet temperature of approximately 500 °C. The test stand utilizes microtube evaporator, an air-cooled microchannel condenser, a plate heat exchanger as regenerator, scroll rotating machines as both expander and pump. To increase the efficiency of the ORC, novel scroll pump design and Oldham Ring scroll expander were installed. An extensive experimental campaign was carried out to map the performance of the expander and the pump along with the overall system performance using R245fa as the working fluid. In addition, thermocouple mesh has been inserted at the upstream and downstream of the evaporator to study the temperature maldistribution from the heat source. The performance was mapped at steady state over a range of operating conditions. The mapped performance has been used to develop a charge-sensitive dynamic model of the ORC system to be predict performance at off-design conditions and develop a control strategy. A discussion on the degradation of the lubricant oil in the system has also been included

Obesity-Associated ECM Remodeling in Cancer Progression

Adipose tissue, an energy storage and endocrine organ, is emerging as an essential player for ECM remodeling. Fibrosis is one of the hallmarks of obese adipose tissue, featuring excessive ECM deposition and enhanced collagen alignment. A variety of ECM components and ECM-related enzymes are produced by adipocytes and myofibroblasts in obese adipose tissue. Data from lineage-tracing models and a single-cell analysis indicate that adipocytes can transform or de-differentiate into myofibroblast/fibroblast-like cells. This de-differentiation process has been observed under normal tissue development and pathological conditions such as cutaneous fibrosis, wound healing, and cancer development. Accumulated evidence has demonstrated that adipocyte de-differentiation and myofibroblasts/fibroblasts play crucial roles in obesity-associated ECM remodeling and cancer progression. In this review, we summarize the recent progress in obesity-related ECM remodeling, the mechanism underlying adipocyte de-differentiation, and the function of obesity-associated ECM remodeling in cancer progression

A 12-Bit, 100 MS/s SAR ADC Based on a Bridge Capacitor Array with Redundancy and Non-Linearity Calibration in 28 nm CMOS

This paper presents a 12-bit, 100 MS/s successive approximation register (SAR) analog-to-digital converter (ADC) based on a bridge capacitor array with redundancy and non-linearity calibration. The differential non-linearity calibration method was proposed to compensate for the linearity, which is degraded by the parasitic capacitance of the bridge capacitor. To reduce the power dissipation and alleviate the settling error of the DAC capacitor array, a hybrid redundant scheme was proposed. A low-power, high-performance SAR ADC was implemented based on the proposed techniques. This SAR ADC prototype was implemented in 28 nm CMOS technology. Measurement results showed that the proposed SAR ADC could achieve a (signal-to-noise distortion ratio) SNDR of 61.46 dB and 58.82 dB at low and Nyquist input frequencies, respectively, resulting in figure of merits (FOMs) of 8.69 fJ/conversion and 11.8 fJ/conversion step, respectively. The SAR ADC core occupied an active area 0.0227 mm2

A Calibration-Free, 16-Channel, 50-MS/s, 14-Bit, Pipelined-SAR ADC with Reference/Op-Amp Sharing and Optimized Stage Resolution Distribution

This paper presents a calibration-free, 16-channel, 14-bit, 50-MS/s, pipelined successive approximation register (pipelined-SAR) analog-to-digital converter (ADC) for ultrasound imaging systems. A reference sharing scheme with reduced buffers is proposed to improve area-and-power efficiency, which is essential for multi-channel systems. Based on this, a three-stage, pipelined-SAR ADC architecture with reference/op-amp sharing and optimized stage resolution distribution is proposed. The prototype ADC is designed in a 0.18-μm process with peripheral circuits integrated, including low-voltage differential signaling (LVDS), bandgap, etc. It achieves a robust and calibration-free performance with 68.25-dB signal to noise and distortion ratio (SNDR) and 82.19-dB spurious-free dynamic range (SFDR), translating into a competitive figure of merit (FoM) of 0.47 pJ/conversion-step among other high-resolution ADCs used in ultrasound applications

A 12-Bit, 100 MS/s SAR ADC Based on a Bridge Capacitor Array with Redundancy and Non-Linearity Calibration in 28 nm CMOS

This paper presents a 12-bit, 100 MS/s successive approximation register (SAR) analog-to-digital converter (ADC) based on a bridge capacitor array with redundancy and non-linearity calibration. The differential non-linearity calibration method was proposed to compensate for the linearity, which is degraded by the parasitic capacitance of the bridge capacitor. To reduce the power dissipation and alleviate the settling error of the DAC capacitor array, a hybrid redundant scheme was proposed. A low-power, high-performance SAR ADC was implemented based on the proposed techniques. This SAR ADC prototype was implemented in 28 nm CMOS technology. Measurement results showed that the proposed SAR ADC could achieve a (signal-to-noise distortion ratio) SNDR of 61.46 dB and 58.82 dB at low and Nyquist input frequencies, respectively, resulting in figure of merits (FOMs) of 8.69 fJ/conversion and 11.8 fJ/conversion step, respectively. The SAR ADC core occupied an active area 0.0227 mm2

A 5.4GHz wide tuning range CMOS PLL using an auto-calibration multiple-pass ring oscillator

A 5.4GHz multiple-pass ring voltage controlled oscillator (VCO) based phase-locked loop (PLL) is described. For the sake of active devices’ sensitivity to process and temperature regarding ring oscillators, an effective automatic frequency calibration scheme is proposed. A new process-independent differential to single (DTOS) is used to adjust control voltage range and loop gain. The chip is implemented in 0.18-um CMOS process and achieves phase noise of -100dBc/Hz@1MHz and a 40% tuning range

An overview of new design techniques for high performance CMOS millimeter-wave circuits

CMOS millimeter-wave integrated circuits are more attractive due to its potential in higher integration with digitalsignal processing blocks and lower cost, compared to SiGe and GaAs. Meanwhile, the cut-off (ft) frequency of MOSFETs is continuously increased along with the scaling down of transistors as predicted with Moore's law. However, CMOS process suffers from high substrate loss and low quality (Q) of passive devices. As a result, circuit performance is hindered with degraded main block such as VCO, divider and LNA. In this paper, some new structures, such as meta-material oscillator, tunable inductors and coupled oscillator, are summarized and demonstrated to overcome these problems in designing high performance millmeter-wave circuits in nano-CMOS.Accepted versio