Dynamic strain aging during the creep and tensile testing of a molybdenum-titanium- carbon alloy

Dynamic strain aging during creep and tensile tests of molybdenum-titanium-carbon alloy

Yielding and fracture in tungsten and tungsten-rhenium alloys

Mechanical properties of tungsten and tungsten rhenium alloy

Influence of boron additions on physical and mechanical properties of arc-melted tungsten and tungsten - 1 percent tantalum alloy

Influence of boron additions on physical and mechanical properties of arc-melted tungsten and of tungsten-tantalum allo

Creep behavior of electron-beam-melted rhenium

Comparison of creep-rupture properties of electron beam-melted polycrystalline and powder- metallurgy rhenium sheets at 2200 to 4200 F and 4 to 40 ks

Lower-cost tungsten-rhenium alloys

Tungsten-rhenium alloys with a substantially more dilute rhenium content have ductilities and other mechanical properties which compare favorably with the tungsten-rhenium alloys having much higher concentrations of the costly rhenium

High-strength tungsten alloy with improved ductility

Alloy combines superior strength at elevated temperatures with improved ductility at lower temperatures relative to unalloyed tungsten. Composed of tungsten, rhenium, hafnium, and carbon, the alloy is prepared by consumable electrode vacuum arc-melting and can be fabricated into rod, plate, and sheet

Effects of Grain Size on the Tensile and Creep Properties of Arc-melted and Electron-beam-melted Tungsten at 2250 Deg to 4140 Deg f

Effects of grain size on tensile and creep properties of arc melted and electron beam melted tungste

Development of a prototype plastic space erectable satellite Quarterly report, Jun. - Aug. 1966

Copper plated high-density polyethylene film evaluation for space erectable satellite desig

ZyON: Enabling Spike Sorting on APSoC-Based Signal Processors for High-Density Microelectrode Arrays

Multi-Electrode Arrays and High-Density Multi-Electrode Arrays of sensors are a key instrument in neuroscience research. Such devices are evolving to provide ever-increasing temporal and spatial resolution, paving the way to unprecedented results when it comes to understanding the behaviour of neuronal networks and interacting with them. However, in some experimental cases, in-place low-latency processing of the sensor data acquired by the arrays is required. This poses the need for high-performance embedded computing platforms capable of processing in real-time the stream of samples produced by the acquisition front-end to extract higher-level information. Previous work has demonstrated that Field-Programmable Gate Array and All-Programmable System-On-Chip devices are suitable target technology for the implementation of real-time processors of High-Density Multi-Electrode Arrays data. However, approaches available in literature can process a limited number of channels or are designed to execute only the first steps of the neural signal processing chain. In this work, we propose an All-Programmable System-On-Chip based implementation capable of sorting neural spikes acquired by the sensors, to associate the shape of each spike to a specific firing neuron. Our system, implemented on a Xilinx Z7020 All-Programmable System-On-Chip is capable of executing on-line spike sorting up to 5500 acquisition channels, 43x more than state-of-the-art alternatives, supporting 18KHz acquisition frequency. We present an experimental study on a commonly used reference dataset, using on-line refinement of the sorting clusters to improve accuracy up to 82%, with only 4% degradation with respect to off-line analysis

A Bandwidth-Efficient Emulator of Biologically-Relevant Spiking Neural Networks on FPGA

Closed-loop experiments involving biological and artificial neural networks would improve the understanding of neural cells functioning principles and lead to the development of new generation neuroprosthesis. Several technological challenges require to be faced, as the development of real-time spiking neural network emulators which could bear the increasing amount of data provided by new generation High-Density Multielectrode Arrays. This work focuses on the development of a real-time spiking neural network emulator addressing fully-connected neural networks. This work presents a new way to increase the number of synapses supported by real-time neural network accelerators. The proposed solution has been implemented on the Xilinx Zynq 7020 All-Programmable SoC and can emulate fully connected spiking neural networks counting up to 3,098 Izhikevich neurons and 9.6e6 synapses in real-time, with a resolution of 0.1 ms