F-DICE: A multiple node upset tolerant flip-flop for highly radioactive environments

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Psycho-educational group therapy in acute psychiatric units: creating a psychosocial culture. An update of spread and effectiveness of a psychosocial intervention in Italian psychiatric wards

The implementation of a Cognitive-Behavioural Group Intervention (CBGI) in Italian general hospital psychiatric units started in the years 2000-2001 in two Italian regions. Over the years it has became more and more popular also in other psychiatric units located in the rest of the country. Based on the "stress-vulnerability-coping" theory, the CBGI is a replicable and innovative psychosocial intervention that promotes the active involvement of inpatients in decisions concerning their individual objectives and care. In the present article, the authors briefly describe this intervention and the main findings regarding its implementation in several psychiatric units in different Regions of Italy. The authors emphasize that such a psychosocial approach to inpatient care is needed because it can produce improved clinical outcomes, reduction in untoward events and increased staff and inpatient satisfaction. However, its introduction and use still represent a major cultural and managerial challenge in our country

N-terminally cleaved Bcl-x(L) mediates ischemia-induced neuronal death

Transient global ischemia in rats induces delayed death of hippocampal CA1 neurons. Early events include caspase activation, cleavage of anti-death Bcl-2 family proteins and large mitochondrial channel activity. However, whether these events have a causal role in ischemia-induced neuronal death is unclear. We found that the Bcl-2 and Bcl-xL inhibitor ABT-737, which enhances death of tumor cells, protected rats against neuronal death in a clinically relevant model of brain ischemia. Bcl-xL is prominently expressed in adult neurons and can be cleaved by caspases to generate a pro-death fragment, ΔN-Bcl-xL. We found that ABT-737 administered before or after ischemia inhibited ΔN-Bcl-xL–induced mitochondrial channel activity and neuronal death. To establish a causal role for ΔN-Bcl-xL, we generated knock-in mice expressing a caspase-resistant form of Bcl-xL. The knock-in mice exhibited markedly reduced mitochondrial channel activity and reduced vulnerability to ischemia-induced neuronal death. These findings suggest that truncated Bcl-xL could be a potentially important therapeutic target in ischemic brain injury

MDR/XDR-TB management of patients and contacts: Challenges facing the new decade. The 2020 clinical update by the Global Tuberculosis Network.

The continuous flow of new research articles on MDR-TB diagnosis, treatment, prevention and rehabilitation requires frequent update of existing guidelines. This review is aimed at providing clinicians and public health staff with an updated and easy-to-consult document arising from consensus of Global Tuberculosis Network (GTN) experts. The core published documents and guidelines have been reviewed, including the recently published MDR-TB WHO rapid advice and ATS/CDC/ERS/IDSA guidelines. After a rapid review of epidemiology and risk factors, the clinical priorities on MDR-TB diagnosis (including whole genome sequencing and drug-susceptibility testing interpretations) and treatment (treatment design and management, TB in children) are discussed. Furthermore, the review comprehensively describes the latest information on contact tracing and LTBI management in MDR-TB contacts, while providing guidance on post-treatment functional evaluation and rehabilitation of TB sequelae, infection control and other public health priorities

A Novel Write-Scheme For Data Integrity In Memristor-Based Crossbar Memories

The memristor is one among the most promising emerging technologies for enabling a new generation of Non Volatile Memories. The memristor operates faster than a Phase Change Memory (PCRAM) and has a simpler structure than a magnetic memory (MRAM), while making possible the design of cross-point structures in crossbars at very high density. The presence of sneak path currents however causes an increase in power consumption and a reduction in data integrity and performance. To overcome this issue a novel write method is proposed to reduce the effects of sneak paths. Extensive SPICE simulations are provided to evidence the advantages of the proposed method

On the design of two single event tolerant slave latches for scan delay testing

This paper proposes two new slave latches for improving the Single Event Upset (SEU) tolerance of a flip- flop in scan delay testing. The two proposed slave latches utilize additional circuitry to increase the critical charge of the flip-flop compared to designs found in the technical literature. The first (second) latch design achieves a 5.6 (2.4) times larger critical charge with 11% (4%) delay and 16 % (9%) power consumption overhead at 32nm feature size as compared to the best design found in the technical literature. Moreover, it is shown that the proposed slave latches have also superior performance in the presence of a single event with a multiple node upset

A single-bit and double-adjacent error correcting parallel decoder for multiple-bit error correcting BCH codes

This paper presents a novel high-speed BCH decoder that corrects double-adjacent and single-bit errors in parallel and serially corrects multiple-bit errors other than double-adjacent errors. Its operation is based on extending an existing parallel BCH decoder that can only correct single-bit errors and serially corrects double-adjacent errors at low speed. The proposed de- coder is constructed by a novel design and is suitable for nanoscale memory systems, in which multiple-bit errors occur at a probability comparable to single-bit errors and double-adjacent errors occur at a higher probability (nearly two orders of magnitude) than other multiple-bit errors. Extensive simulation results are reported. Compared with the existing scheme, the area and de- lay time of the proposed decoder are on average 11% and 6% higher, but its power consumption is reduced by 9% on average. This paper also shows that the area, delay, and power overheads incurred by the proposed scheme are significantly lower than traditional fully parallelized BCH decoders capable of correcting any double-bit errors in parallel