Développement d'architectures avancées pour communications ultra large bande (UWB) dans des applications bas débit

Nombre d'applications nécessitent un lien de communication sans fil présentant une faible consommation électrique, sans requérir de débits élevés. La technologie basée sur la transmission de signaux impulsionnels UWB dispose de bonnes propriétés intrinsèques permettant non seulement d'envisager la mise en œuvre de solutions peu complexes au niveau de l'émetteur-récepteur, mais aussi d'exploiter à des fins de radiolocalisation la résolution temporelle inhérente à la largeur de bande disponible. Cette technologie a d'ailleurs été plébiscitée au sein du groupe IEEE 802.15.4a qui a été chargé de définir une couche physique alternative pour les WPAN bas débit. C'est dans ce contexte de recherche technologique et de normalisation que s'inscrivent ces travaux de thèse, avec pour objectif la définition d'une architecture de récepteur consommant peu, et compatible avec la norme en cours d'élaboration. En premier lieu, nous caractérisons les signaux UWB et développons un modèle d'impulsion prenant en compte les principaux paramètres de la couche physique intervenant dans la puissance rayonnée (largeur de bande, densité spectrale, fréquence de répétition des impulsions, etc.). Nous étudions ensuite l'influence du canal de propagation et modélisons de manière statistique plusieurs grandeurs nécessaires à l'établissement d'un bilan de liaison réaliste (distribution des amplitudes reçues, répartition de l'énergie, etc.). À la lumière de ces études, nous explorons et comparons différentes architectures de réception (performance, complexité, robustesse aux trajets multiples, etc). Enfin, la solution retenue, comprenant également un algorithme de synchronisation, est présentée en détails.Many applications like sensor networks require a wireless link to transfer data, not necessarily with a high speed rate, but with very low power consumption. The Impulse Radio - Ultra Wideband technology benefits from intrinsic properties that enable to develop low-complexity transceiver solutions. It also takes advantage of the fine temporal resolution that inherently results from the wide available bandwidth, hence providing appealing radiolocation capabilities. For these two main reasons, UWB technologies were strongly supported when the IEEE 802.15.4a task group started defining an alternative physical layer (PHY) for Wireless Personal Area Networks (WPAN). The work presented in this thesis took place in this double context of technological research and standardization, aiming at a low-complexity receiver architecture compliant with the on-going standard. Firstly, UWB signals are characterized and an analytical pulse model is proposed. It takes into account the main PHY parameters entering into the radiated power, such as bandwidth, power spectral density, pulse repetition frequency, etc. The propagation channel influence is then considered. Different statistical studies based on IEEE channel models are proposed, concerning energy repartition, small scale fading, pulse magnitude distribution and correlation properties. Subsequently, the different kinds of receiver architectures are described and compared in terms of performance, complexity, robustness to multi-paths, etc. Finally, the most relevant features of the 802.15.4a standard and the complete solution selected for implementation are detailed, including a synchronization algorithm compliant with IEEE preambles.PARIS-Télécom ParisTech (751132302) / SudocSudocFranceF

A multiagent approach for an UWB location embedded software architecture

International audienc

Utilisation de la phase d'analyse de la méthode Diamond pour concevoir un système de radiolocalisation,

National audienc

A Hardware Instruction Generation Mechanism for Energy-Efficient Computational Memories

International audienceIn the Computing-In-Memory (CIM) approach, computations are directly performed within the data storage unit, which often results in energy reduction. This makes it particularly well fitted for embedded systems, highly constrained in energy efficiency.It is commonly admitted that this energy reduction comes from less data transfers between the CPU and the main memory.Nevertheless, preparing and sending instructions to the computational memory also consumes energy and time, hence limiting overall performance.In this paper, we present a hardware instruction generation mechanism integrated in computational memories and evaluate its benefit for Integer General Matrix Multiplication (IGeMM) operations.The proposed mechanism is implemented in the computational memory controller and translates macro-instructions into corresponding micro-instructions needed to execute the kernel on stored data. We modified an existing near-memory computing architecture and extracted corresponding energy consumption figures using post-layout simulations for the complete SoC. Our proposed architecture, NEar memory computing Macro Instructions Kernal Accelerator (NeMIKA), provides an 8.2x speed-up and a 4.6x energy consumption reduction compared to a state-of-the-art CIM accelerator based on micro-instructions, while inducing an area overhead of only 0.1%

Flexible, Cost-Efficient, High-Throughput Architecture for Layered LDPC Decoders with Fully-Parallel Processing Units

International audience—In this paper, we propose a layered LDPC decoder architecture targeting flexibility, high-throughput, low cost, and efficient use of the hardware resources. The proposed architecture provides full design time flexibility, i.e., it can accommodate any Quasi-Cyclic (QC) LDPC code, and also allows redefining a number of parameters of the QC-LDPC code at the run time. The main novelty of the paper consists of: (1) a new low-cost processing unit that merges in an efficient way the logical functionalities of the Variable-Node Unit (VNU) and the A Posteriori Log-Likelihood Ratio (AP-LLR) unit, (2) a high speed, low-cost Check-Node Unit (CNU) architecture, which is executed twice in order to complete the computation of the check-node messages at each iteration, (3) a splitting of the iteration processing in two perfectly symmetric stages, executed in two consecutive clock cycles, each one using exactly the same processing resources; the processing load is perfectly balanced between the two clock cycles, thus yielding an optimal clock frequency. Synthesis results targeting a 65nm CMOS technology for a (3, 6)-regular (648, 1296) Quasi-Cyclic LDPC code and for the WiMax (1152, 2304) irregular QC-LDPC code show significant improvements in terms of area and throughput compared to the baseline architecture discussed in this paper, as well as several state of the art implementations

A near-instantaneous and non-invasive erasure design technique to protect sensitive data stored in secure SRAMs

International audienceOn-chip memories, and in particular SRAMs, are among the most critical components in terms of data security because they might contain sensitive data such as secret keys. Whenever a tampering event is detected, one should be able to erase efficiently and rapidly the full content of a memory holding such sensitive data, but current solutions based on simple power-off leadto very long erasure times. In this paper, we present a non-invasive design technique based on an innovative mechanism to remove electric charges from SRAM bitcells still powered on, beforerefreshing them with a new content not correlated with the previous one. The particularity of this novel hardware countermeasure is to be natively compatible with any SRAM circuit designed from pushed-rule foundry bitcells. We have designed and characterized an 8kB SRAM in 22nm FD-SOI process technology exploiting the proposed security strategy demonstrating an erase operation accomplished in the nanosecond time scale (versus 295$\mu$s with the conventional power-off solution) at the cost of an additional area of less than 5%. We have also shown that our solution is more efficient than a solution without prior erasure consisting in writing identical data to all memory addresses in a single clock cycle (1 ns). The use of the latter drops the ratio of zeroized addresses at 92%, while increasing the operating energy consumption by 2.1x under nominal operating conditions