Speeding-Up Expensive Evaluations in High-Level Synthesis Using Solution Modeling and Fitness Inheritance

High-Level Synthesis (HLS) is the process of developing digital circuits from behavioral specifications. It involves three interdependent and NP-complete optimization problems: (i) the operation scheduling, (ii) the resource allocation, and (iii) the controller synthesis. Evolutionary Algorithms have been already effectively applied to HLS to find good solution in presence of conflicting design objectives. In this paper, we present an evolutionary approach to HLS that extends previous works in three respects: (i) we exploit the NSGA-II, a multi-objective genetic algorithm, to fully automate the design space exploration without the need of any human intervention, (ii) we replace the expensive evaluation process of candidate solutions with a quite accurate regression model, and (iii) we reduce the number of evaluations with a fitness inheritance scheme. We tested our approach on several benchmark problems. Our results suggest that all the enhancements introduced improve the overall performance of the evolutionary search

Impact of Multicycled Scheduling on Power-Area Tradeoffs in Behavioural Synthesis

Multicycling is a widely investigated technique for performance optimisation in behavioural synthesis. It allows an operation to execute over two or more control steps with the aim of increasing the performance and/or minimising the power consumption. This paper presents a new time-constrained scheduling (TCS) algorithm that takes into account the combined influence of clock period and the multicycled functional units execution time on the quality of the schedules in terms of power and area. It is shown that it is possible to produce a set of solutions that have similar power consumptions, however differ in terms of resource requirements, yet meeting the imposed real-time constraint. Furthermore, extensive experiments on behavioural benchmarks show that the proposed approach is capable of obtaining schedules with single supply domain that have identical resource requirements and comparable power consumption to schedules obtained using multiple supply voltages, further reducing the design complexity

Algorithms for scheduling, allocation and binding in high level synthesis

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ARGEN: A behavioral level compiler for hardware realisation of DSP systems

This paper introduces ARGEN, a compiler that translates behavioural level description of DSP algorithms into efficient data path structures expressed in VHDL. ARGEN is based on novel data path synthesis algorithms that utilise stochastic techniques and hence result in low computational complexity and excellent solution quality. These features make it suitable for application to a wide range of practical DSP applications including FIR, IIR digital filters, compression algorithms and DCTs used in video applications

FPGA Implementation of high performance FIR Filters

This paper describes the design and implementation of high performance, high speed linear phase FIR filters using FPGA technology. To demonstrate the design process, the implementation of a 64 tap filter with 60dB attenuation at 0.28fs, 12dB attenuation at 0.25fs and a passband ripple of <0.02dB up to 0.22fs is included. The filter with 10bit signal and 8bit coefficients has been realised on a Xilinx XC4006E device and operates at a sampling frequency of 1.4MHz

Design and implementation of digital systems for automatic control based on behavioral descriptions

This paper describes how top-down digital system design is achieved, starting with the system behavioural description down to gate-level realisation using VHDL. This process is demonstrated through the design of an 8-bit PID controller based on resource constrained scheduling. Synthesis results are included to illustrate the efficiency of this design approach

Reduction of latency and resource usage in bit-level pipelined data paths for FPGAs

Pipelining of data path structures increases the throughput rate at the expense of enlarged resource usage and latency unless architectures optimised towards specific applications are used. This paper describes a novel methodology for the design of generic bit-level pipelined data paths that have the low resource usage and latency of specifically tailored architectures but still allow the flexible trade-off between speed and resource requirements inherent in generic circuits. This is achieved through the elimination of all skew and alignment flip-flops from the data path whilst still maintaining the original pipelining scheme, hence allowing more compact structures with decreased circuit delays. The resulting low latency is beneficial in the realisation of all recursive signal processing applications and the reduced resource usage enables particularly the efficient FPGA realisation of high performance signal processing functions. The design process is illustrated through the high level-based FPGA realisation of a 9th-order wave digital filter, demonstrating that high performance and efficient resource usage are possible. For example, the implementation of a digital filter with 10-bit signal word length and 6-bit coefficients using a Xilinx XC4013XL-1 device supports sample rates of 2.5MH