IGBT Scaling Principle Toward CMOS Compatible Wafer Processes

A scaling principle for trench gate IGBT is proposed. CMOS technology on large diameter wafer enables to produce various digital circuits with higher performance and lower cost. The transistor cell structure becomes laterally smaller and smaller and vertically shallower and shallower. In contrast, latest IGBTs have rather deeper trench structure to obtain lower on-state voltage drop and turn-off loss. In the aspect of the process uniformity and wafer warpage, manufacturing such structure in the CMOS factory is difficult. In this paper, we show the scaling principle toward shallower structure and better performance. The principle is theoretically explained by our previously proposed “Structure Oriented” analytical model. The principle represents a possibility of technology direction and roadmap for future IGBT for improving the device performance consistent with lower cost and high volume productivity with CMOS compatible large diameter wafer technologies

Scaling Rule for Very Shallow Trench IGBT toward CMOS Process Compatibility

2012 24th International Symposium on Power Semiconductor Devices and ICs (ISPSD 2012), June 3-7, 2012, Bruges, BelgiumDeep trench gate is used for latest IGBT to improve device performance. By large difference from deep submicron CMOS structure, there is no process compatibility among CMOS device and trench gate IGBT. We propose IGBT scaling rule for shrinking IGBT cell structure both horizontally and vertically. The scaling rule is theoretically delivered by structure based equations. Device performance improvement was also predicted by TCAD simulations even with very shallow trench gate. The rule enables to produce trench gate IGBT on large diameter wafer in CMOS factory with superior productivity

Real-time Failure Monitoring System for High Power IGBT Under Acceleration Test Up to 500 A Stress

Real-time failure monitoring system for IGBT module was demonstrated under 500 A power cycling test. The system successfully captured internal phenomena occurred in interface regions of the device under test. Moreover, we proposed realtime failure analysis method by combining the real-time monitoring and image processing techniques. This failure analysis method enables to distinguish the place where degradation occurs in DUT and also trace internal degradation process to failure.2014 IEEE 26th International Symposium on Power Semiconductor Devices & IC\u27s (ISPSD), Jun 15-19, 2014, Hilton Waikoloa Village, Hawaii, US

Ultrafast Lateral 600 V Silicon SOI PiN Diode with Geometric Traps for Preventing Waveform Oscillation

An ultrafast lateral silicon PiN diode with traps is proposed using a silicon-on-insulator (SOI) substrate with traps. The proposed diode successfully suppresses waveform oscillation because the trapped hole suppresses electric field penetration and prevents the oscillation trigger known as “dynamic punch-through.” Because of the short current path caused by the oscillation prevention, the reverse recovery speed was higher and the reverse recovery loss was strongly reduced. The proposed trap structure and design method would contribute to performance improvement of all power semiconductor devices including IGBTs and power MOSFETs

Real Time Monitoring System for Internal Process to Failure of High Power IGBT

A real time failure analysis system for widely used high power IGBT modules is proposed, which enables to inspect internal process to failure of the devices under power stress test as a movie. This system was realized by combining a scanning acoustic tomography (SAT/SAM), power stress controlling, device cooling, water jet system and chip temperature monitoring. This system successfully obtained internal images of a DUT under the load current of 200A.2013 International Conference on Solid State Devices and Materials (SSDM2013), September 24-27, 2013, Hilton Fukuoka Sea Hawk, Fukuoka, Japa

Scattering Parameter Approach to Power MOSFET Design for EMI

Electromagnetic interference (EMI) noise byavalanche oscillations is the major barrier to improve powerdevice performance. Especially the oscillations of three-terminaldevices are more complex than two-terminal devices in point ofthe mutual relationship between devices and external circuit. Scattering parameter (S-parameter) under avalanche condition is obtained to establish stable-unstable criterion with stability factor (K-factor). The stable-unstable criterion clearly indicates the unstable frequency range with each change in MOSFET design. In addition the oscillation mechanism on power MOSFET is modeled with junction capacitance, which is the same as that of diode. For EMI suppression, resonant frequency of external circuit has to be different from unstable frequency of MOSFETs.2012 24th International Symposium on Power Semiconductor Devices and ICs (ISPSD 2012), June 3-7, 2012, Bruges, Belgiu

Ultra Low Loss Trench Gate PCI-PiN Diode with VF<350mV

PiN diode forward voltage drop was reduced to as low as 325mV by the pulsed carrier injection (PCI) mechanism with trench MOS gate as the integrated injection control switch. The conventional PiN diodes have voltage drop of about 0.8V which is equivalent to 1%-2% energy loss in home appliances. The proposed PCI-PiN diode reduces the loss by more than 50% and the diode structure has process compatibility to conventional IGBTs and trench MOSFETs for easy implementation into mass production. The authors also confirmed PCI concept with the experiment with BSIT.2011 23rd International Symposium on Power Semiconductor Devices & Ics (ISPSD. 2011), May 23?26, 2011, San Diego, California, US

Internal Degradation Monitoring of Power Devices During Power Cycling Test

A technique to monitor internal degradation to failure of power devices in real time was proposed. Required components for this technique are (1) non-destructive inside imaging, (2) power stress control and (3) device cooling. We constructed the system with scanning acoustic tomography (SAT), DC power supply controlled by own made program and water cooling system, respectively. In the case of a TO-3P packaged MOSFET, propagation of internal degradations to failure was successfully recorded as time series data by using this system. At the present time, the system is modified for high power and large size IGBT modules.8th International Conference on Integrated Power Electronics Systems (CIPS 2014), February 25-27, 2014, Nuremberg, German

IGBT Avalanche Current Filamentaion Ratio: Precise Simulations on Mesh and Structure Effect

Current filamentaion effect with dynamic avalanche during turn-off transient in IGBT has been discussed for years. In the prior papers, the possibility of device failure has been reported based on TCAD simulation and simulation results have shown that variety of filamentation phenomena exist for conditions assumed in each simulation. It is discussed in this paper, for the first time, that the relationship of filamentation current concentration strength to device design parameters and categorizes filamentation phenomena, introducing current filamentation ratio (CFR). In the paper, guidelines for appropriate mesh pattern selection are also described to ensure the validity of simulation results.ISPSD 2016 28th International Symposium on Power Semiconductor Devices and ICs., Jun 12-16, 2016, Žofín Palace, Prague, Czech Republi

Full Digital Short Circuit Protection for Advanced IGBTs

A full digital short circuit protection method for advanced IGBTs has been proposed and experimentally demonstrated for the first time. The method employs combination of digital circuit, the gate charge sense instead of the conventional sense IGBT and analog circuit configuration. Digital protection scheme has significant advantages in thevprotection speed and flexibility.2011 23rd International Symposium on Power Semiconductor Devices & Ics (ISPSD. 2011), May 23?26, 2011, San Diego, California, US