Synchronous protocol for real-time communications in intelligent vehicle

International audienceIn this paper we describe the design and implementation of a real-time distributed executive for an obstacles detection system, PRO-CHIP, using synchronous communication protocol. The synchronous protocol permits to preserve the consistency specification of the application algorithms. The executive model is based on generic executive kernel which contains a portable set of services (high level system) and very fast microkernel (low level system) which manages concurrent processes and schedules their execution. This executive provides the maximum portability, preserves the efficiency of the system, and guarantees real-time constraints

Environnement de Conception, de Validation, et de Prototypage Rapide des Systèmes Multiprocesseurs sur Puce, pour les applications de traitement de signal

National audienc

Designing reliable processor cores in ultimate CMOS and beyond: A double sampling solution

International audienceThe double sampling paradigm is an efficient method to protect the circuits against soft-errors. But the data that are going out of the area protected by double sampling are still vulnerable. In this paper we proposed an architectural solution that uses three latches to remove those constraints and protect the area outside the double sampling domain without adding a buffer stage

Conception des Systèmes sur puce à partir de Matlab\Simulink

National audienc

Design Space Exploration for Hardware/Software Codesign of Multiprocessor

In this paper, we present a new methodology to rapidly explore the large design space encountered in hardware /software systems. The proposed methodology is based on a fast and accurate estimation approach. It has been implemented as an extension to a hardware/software codesign flow to enable the exploration of a large number of multiprocessor architecture solutions from the very start of the design process. The effectiveness of this approach is illustrated by a significant application example

Error Rate Prediction of Applications Implemented in Multi-Core and Many-Core Processors

International audienc

Detailed and highly parallelizable cycle-accurate network-on-chip simulation on GPGPU

International audienceAs the number of processing elements in modern chips keeps increasing, the evaluation of new designs will need to account for various challenges at the NoC level. To cope with the impractically long run times when simulating large NoCs, we introduce a novel GPU-based parallel simulation method that can speed up simulations by over 250×, while offering RTL-like accuracy. These promising results make our simulation method ideal for evaluating future NoCs comprising thousands of nodes

SEU Impact in Processor's Control-Unit: Preliminary Results Obtained for LEON3 Soft-Core

International audienceThe miniaturization issues from the advanced integrated circuit manufacturing technologies lead to increase the probabilities of single node upset and multiple upsets errors of neighbor nodes. The study of such conjecture is mandatory to specify the protection requirements. This paper deals with the study of such single and multiple errors due to the impact of a single particle in the control unit of complex devices such as processors. Because the layout of the studied device cannot be anticipated, the node’s neighborhood is thus unknown. To deal with this issue, this work presents the results of both exhaustive and random fault-injection experiments performed at register transfer level (RTL) and targeting the control bits of LEON3 processor. Fault injection is achieved by means an automatic netlist fault injection tool called NETFI-2

A Real Time Multiprocessor Application Development Environment Design And Implementation

International audienc